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Study on FIR Filter Based on Residue Number System

Author: ChenJianWen
Tutor: YaoRuoHe
School: South China University of Technology
Course: Microelectronics and Solid State Electronics
Keywords: Residue number system RNS FIR filter Modulo multiplier Modulo adder Converter between binary and residue Chinese Remainder Theorem
CLC: TP332.22
Type: PhD thesis
Year: 2010
Downloads: 180
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Finite impulse response (FIR) digital filters have attracted a great deal of interest because of their inherent stable structures. The major disadvantage of an FIR design is that usually a large number of multiplications and additions for nonzero terms must be executed during a shorter time in order to adequately control the frequency response of the filter. With the result that FIR filters must be of high-speed and high-efficient ability of the data processing. However, FIR filters using traditional 2’s complement system cannot support real-time and high-precision filter under the ultra-high informational flows. With inherent parallel, modularity and fault-tolerant performance, residue number systerm (RNS) opens a window for the design of high-performance FIR filters.Recently, the existing problems of FIR filters using RNS are that, firstly, the computational ability of each modular channel is uneven, this leads to a bad balance between each channels’ latency. Secondly, the architecture for residue-to-binary converters are very complex, this leads to a large overhead for area and delay. All above set blocks in front of the development of RNS FIR filters. In this paper, the following researches on RNS FIR filters are proposed:To upgrade the overall performance of RNS FIR filters, efficient and multi-channel moduli set are selected. The selection of the moduli set plays a critical role in the improvement on the performance of RNS FIR filters. Based on Chinese Remainder Theorem (CRT), five principles obeyed in the selection of moduli set are proposed. According to these principles, the moduli set {2n?1, 2n, 2n+1, 2n+1-1, 2n-1-1} is used to design RNS FIR filters in this paper. This five-moduli set has a dynamic range of (5n-1) bits, this is sufficient to satisfy the demand of the popular digital signal processing applications. Moreover, each modulus has the form of 2n or 2n±1, these moduli forms make the hardware implementation of modular arithmetic easier and more efficient. For a given dynamic range, the wordlength of each modulus in this moduli set is shorter and the balance between moduli is better than other moduli sets.To upgrade the part performance of RNS FIR filters, efficient and high-speed modulo adders suitable to RNS FIR filters are selected based on exploring variable algorithms for modulo adders. At present, most high-speed adders adopt parellel prefix computation of carry chain, which can be directly applied to modulo 2n adders. Aimed at modulo 2n-1 adders with double representations of zero, a modulo 2n-1 addition algorithm with a single representation of zero is proposed, the proposed algorithm depart from the traditional approach of modulo 2n-1 addition by setting the input carry in the first stage of the additon to one. The resulting architectures offer significant speedup in a modulo 2n-1 addition, although their area are not reduced. To avoid (n+1)-bit circuits in modulo 2n+1 adders, based on the current efficient architecture for modulo 2n+1 addition of operands that follow the diminished-1 representation, a new architecture for modulo 2n+1 addition of operands that follow the weighted representation is proposed. These modulo 2n+1 adders are achieved by merging conversions between diminished-1 and weighted and diminished-1 adders on algorithm level. The delay of this modulo 2n+1 addition approximates to the delay of modulo 2n or 2n-1 addition. The modulo 2n+1 channel using this addition algorithm can balance better with modulo 2n and 2n-1 channels.Efficient conversion algorithms between residue and binary are proposed. These conversion algorithms aim at the selected moduli set in this paper. Aimed at the problem of the large delay in modulo 2n+1 operation, an efficient binary-to-residue conversion algorithm is proposed, this algorithm is achieved by using diminished-1 adder as adder stage, rather than weighted adder, this leads to a small difference between modulo 2n+1 channel and other moduli channels. The conversion from residue to weighted binary representation plays an important role in the residue number system. Based on CRT, a new residue-to-binary converter using arbitrary moduli set is proposed. The new converter uses the difference-correction algorithm for the conversion output and eliminates the large modulo arithmetic. The sizes of the multipliers and modular multipliers in the new converter are small, thereby reducing the area and delay of the proposed converter. The analytic results indicate that the new converter is more area-time efficient than the published converters using CRT. Based on this universal residue-to-binary conversion, an efficient and parallell conversion algorithm from residue to weighted binary representation is proposed. The proposed conversion using the five-moduli set {2n-1, 2n, 2n+1, 2n+1-1, 2n-1-1} deals with the five moduli in parallel and eliminates all the terms whose values are greater than the dynamic range, thereby reducing the area and delay of the proposed converter. The hardware implementation of the proposed converter employs adders as the primitive operators.Classical modulo 2n and 2n-1 multipliers based on radix-4 Booth recoding and Wallace tree are presented in this paper. An efficient and high-speed diminished-1 modulo 2n+1 multiplication algorithm is proposed. Based on this multiplication algorithm, area-time efficient modulo (2n+1) multipliers are proposed. The result and one operand for the new modulo multipliers use weighted representation, while the other uses the diminished-1. By using the radix-4 Booth recoding, the number of the partial products of the new multipliers is the least among all modular multipliers, and the new multipliers offer enhanced operation speed and more compact area among all the efficient existing solutions. These lead to a better balance between modular channels.Finally, a group of high-speed, high-precise and low power dissipation RNS FIR filters are implemented in this paper by using the proposed algorithms and modules. To prove significant improvement, comparisons with FIR filters using traditional 2’s complementation system (TCS) are made, and the results indicate that RNS FIR filters offer the best implementation among all the existing solutions for high order and high precise FIR filters.

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CLC: > Industrial Technology > Automation technology,computer technology > Computing technology,computer technology > Electronic digital computer (not a continuous role in computer ) > Arithmetic unit and the controller (CPU) > Arithmetic unit > Multiplication , division control
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