Dissertation 

About 1196 item dissertation in line with TP332,Arithmetic unit and the controller (CPU) query results,the following is 1 to 50(Search took 0.062 seconds)

  1. Research on the WCET Analysis of Real-time Systems in Multi-core Platform,ChenFangYuan/National University of Defense Science and Technology,0/34
  2. Energy-efficient Real-time Scheduling for Multi-core and Multiprocessor System,ZhangDongSong/National University of Defense Science and Technology,0/103
  3. Design and Optimization of the Pipeline for the64-bits RISC Stream Core,ZhaoQi/National University of Defense Science and Technology,0/16
  4. Design and Implementation of the Arithmetic Units for64-bit Stream Core,MeiJiaXiang/National University of Defense Science and Technology,0/19
  5. The Design and Implementation of High-performance fixed-point Arithmetic Unit for SIMD DSP,LiGuoQiang/National University of Defense Science and Technology,0/17
  6. Design of On-chip Data Channel between the SPARCV8and the DSP,WangXing/National University of Defense Science and Technology,0/12
  7. The Design and Implementation of YHFT-DX Register File,FengGuoZhu/National University of Defense Science and Technology,0/4
  8. Design and Implemtation of BP Component and Shuffle Unit in YHFT-Matrix Processor,ZhouFeng/National University of Defense Science and Technology,0/5
  9. The Design and Implementation of High Performance EMIF and DDR2Interface on YHFT-Matrix Processor,ZengSi/National University of Defense Science and Technology,0/7
  10. The Research and Design of EDMA Interface in High-performance DSP YHFT-QMBase,ChenShiChao/National University of Defense Science and Technology,0/8
  11. The Design and Implementation of Custom for Low-delay Register,ZhaoZongHao/National University of Defense Science and Technology,0/6
  12. Key Techniques Research of Memory in Homogeneous General Purpose Stream Processor,ZuoYinPi/National University of Defense Science and Technology,0/12
  13. Design and Verification of FPGA-based DDR3SDRAM Controller,MengXiaoDong/National University of Defense Science and Technology,0/168
  14. Design and Implementation of the Instruction Dispatch Unit with Emulation/Test Support,WangHuiLi/National University of Defense Science and Technology,0/2
  15. The Optimization of Memory Controller for High Performance CPU,WangHongYan/National University of Defense Science and Technology,0/14
  16. The Study and Implementation of Clock Structure for Fishbone,ZengYanFei/National University of Defense Science and Technology,0/8
  17. Design and Implementation of Vectorized FFTs on the YHFT-Matrix,HuangJunHui/National University of Defense Science and Technology,0/2
  18. Design and Implementation the Key Algorithm of MIMO-OFDM System Base on YHFT-Matrix,ZengYongTao/National University of Defense Science and Technology,0/5
  19. Research on Key Techniques on Design of Data-driven Asynchronous Microprocessors,RenHongGuang/National University of Defense Science and Technology,0/25
  20. Research on the Key Techniques of Dynamic Soft Error Tolerance Design on High Performance Microprocessor,ChengYu/National University of Defense Science and Technology,0/51
  21. The Simulation and Implementation of Processor Register Level for OpenRISC,TangJianQiu/Hunan University,0/4
  22. Design Heterogeneous Multi-core System Based on Soclib Platfrom and Performance Testing,FanXiangZuo/Harbin Institute of Technology,0/33
  23. Research of Sparc-rtems Driving Technology for Java Accelerating System,WangYongShuang/Harbin Institute of Technology,0/13
  24. Research on Instruction Dynamic Mapping Algorithm of EDGE Architecture,GaoJun/Harbin Institute of Technology,0/5
  25. The Benchmark Test and Performance Optimization of Java Processor Heterogeneous Multi-core Systems,LiXu/Harbin Institute of Technology,0/14
  26. Sensitivity Analysis for Processor Based on VHDL Fault Injection,WuZhenPing/Harbin Institute of Technology,0/10
  27. Design of PXI Express Controller Based on PowerPC,LiHongJie/Harbin Institute of Technology,0/23
  28. Design and Implement of the ARM JTAG Emulator,HuangHaiQuan/University of Electronic Science and Technology,0/23
  29. Based on Configuration Technology of Touch Screen Controller Design and Realization,SongYongBo/Tianjin University,0/5
  30. Design and Implementation of32-bit RISC Microprocessor Based on FPGA,ZhengYongGui/Hebei University of Technology,0/73
  31. Research and Design of32-bit and Five-stage Pipelined CPU Based on FPGA,MiHaiXiao/Hebei University of Technology,0/76
  32. Research and Design of54b×54b Redundant Binary Multiplier,WangXiaoZuo/Nanjing University of Aeronautics and Astronautics,0/1
  33. Design and Application of Register File in a High Performance DSP,LiuRenChang/Harbin Institute of Technology,0/3
  34. Research on Shared L2Cache Management Mechanism Based on CMP,ZhangJie/Harbin Engineering University,0/9
  35. Research of RTEMS Embedded Operating System with Support for Muliticore Processor,NiuYingZuo/Harbin Engineering University,0/33
  36. Research of IRQ Load Balancing for SMP Virtual Machines,LuZhiQiang/Huazhong University of Science and Technology,0/3
  37. Real-time Task Scheduling Strategies for Multimedia Stream Computing on Heterogeneous Multicore Systems,ZhouHuiJiao/Huazhong University of Science and Technology,0/10
  38. Research of Parallel Method for GPU-based Multiple Sequence Relevance Analysis,ZhangQiongYao/Huazhong University of Science and Technology,0/5
  39. Research on Verification Techniques of High-performance ESCA Co-processor,DengChengNuo/Huazhong University of Science and Technology,0/3
  40. Design and Verification of CORDIC-based FFT Processor,MaChao/Harbin Engineering University,0/34
  41. The Research and Design of RISC Microprocessor Soft Core,ZhuShuangBing/Hubei University,0/5
  42. ExtCSS: a Preprocessor for Cascading Style Sheet,GuoZhiWei/Sun Yat-sen University,0/1
  43. Research on Kev Techniques of Conditional Branch Processing,ChenChen/Zhejiang University,0/21
  44. Research on Power Optimization of Cache Architecture Design,XiangXiaoYan/Zhejiang University,0/22
  45. Research on Task Scheduling for Heterogeneous Multi-core Processors,ChenWenYan/Hunan University,0/6
  46. Embedded Processor Microarchitecture Optimization,LiuYong/Zhejiang University,0/2
  47. Research of Embedded Application-level Software Performance Monitoring based on Multi-core Environment,WanWei/Huazhong University of Science and Technology,0/2
  48. Research and Implementation of Fast Fourier Transform by Using Custom Instruction Based NiosⅡ Processor,TianYe/Xi'an Optics and Fine Mechanics,0/11
  49. Research of Wavefront Reconstruction System for Adaptive Optics Based on Multi-core DSP,WuMin/Xi'an Optics and Fine Mechanics,0/11
  50. Optimizations of Memory Subsystem for Chip Multiprocessor Systems,LiJianHua/University of Science and Technology of China,0/35

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