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High-Speed and High-Performance Hardware Implementation of the 3GPP Algorithm KASUMI

Author: ZhaoXue
Tutor: GuoShuXu
School: Jilin University
Course: Circuits and Systems
Keywords: KASUMI algorithm FPGA Throughput Pipeline technology
CLC: TN925
Type: Master's thesis
Year: 2006
Downloads: 83
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Abstract


One kind of digital signal processing must be finished in thelimited time.If the high speed CPU is used, it can not finish therequired computing. If we use KASUMI algorithm to process thesesignals, we must use FPGA devices or ASIC.Since the designing andproducing periods of ASIC are very long and the products areexpensive, we introduce one high-speed and high-performance FPGAimplementationoftheKASUMIalgorithm.Within the securityarchitecture of the 3GPPsystem there are twostandardized algorithms: A confidentiality algorithm f8, and anintegrity algorithm f9. Each of these algorithms is based on theKASUMIalgorithm.KASUMIis ablock cipherthat produces a64-bitoutputfroma64-bitinputunderthecontrolofa128-bitkey.In this paper one high-speed and high-performance FPGAimplementationoftheKASUMIalgorithmispresented.Itoutperformsany previous published KASUMI implementation in terms of clockfrequency fmax and throughput. The throughput achieves 6346.88Mbpsat99.17MHz.The design uses the pipeline technique and a FPGA device. Thedesigns are implemented by using VerilogHDL. All the VerilogHDLcode has been simulated and verified by using the test vectors,provided by the 3GPP standard [3]. Quartus II 4.1 tool and Stratix IIare used for synthesis, implementation and timing analysis. Stratix IIdevices are the latest in high-density, high-performance FPGA fromAltera.Supposed architecture uses eight level pipeline techniques inordertomaximizespeedandthroughput.Thereare9pipelineregistersin the architecture. The registers in the first round are used to registerinput data. Other registers temporally store the output of the previousround.Anew64-bit data blockcanbeloadedeveryclockcycle. Intheninth clock cycle, processing of the first 64-bit data block is finished.After the ninth clock cycle, every clock cycle processing of a new64-bitdatablockcanbefinished.Thearchitecturehasthepossibilitytoprocess 8 data blocks simultaneously in one clock cycle. So thisarchitecture can maximize throughput.Implementation of key schedule[2] also uses pipeline technique in order to cooperate with thisarchitecture.

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CLC: > Industrial Technology > Radio electronics, telecommunications technology > Wireless communications > Radio relay communications,microwave communications
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