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The Design and FPGA Verification of Embedded UART Based on VHDL/FPGA

Author: ZhuQin
Tutor: QianMin
School: Suzhou University
Course: IC Engineering
Keywords: RS232 SOC UART IP core The state machine FPGA
CLC: TN47
Type: Master's thesis
Year: 2011
Downloads: 162
Quote: 0
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Abstract


As VLSI design technology and deep sub-micron manufacturing technology development , system integration chip design methods have become the future mainstream IC industry , and IP core technology as the most typical SOC design effective method development by the industry attention. Universal Asynchronous Receiver Transmitter UART as an input / output system is an important component of the system is very commonly used in SOC IP core . This topic using Top-down design methodology , through the system functions into modules to be designed . Including the transmission module, receiver module , interrupt module , modem module , the various functional modules and the entire system design and simulation software Xilinx ISE9.1i . Final details of the design of FPGA-based hardware verification and validation methods . Test results show that the design is correct , good function. Paper is divided into six chapters , of which the third, fourth and fifth chapter is the focus of this article section. Mainly on the research methods , content and results. Thesis by analyzing the current domestic situation and development of integrated circuits IP core importance is demonstrated to design a UART IP soft core meaning , and finally summarizes the topic work and the results achieved .

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CLC: > Industrial Technology > Radio electronics, telecommunications technology > Microelectronics, integrated circuit (IC) > LSI,ultra LSI
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