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FPGA-based research portable disturbance recorder

Author: YuanTengFei
Tutor: ChengQiong
School: Hubei University of Technology
Course: Power Electronics and Power Drives
Keywords: Disturbance FPGA DSP Builder NIOS II
CLC: TM935
Type: Master's thesis
Year: 2010
Downloads: 80
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Abstract


With the growing demand for electricity , power systems toward complicate or escalate and intelligent trend , therefore, the power system fault analysis also appears to be increasingly important . Power system fault analysis as essential to the development of the power system fault recording technology in the process has made considerable progress. However, the existence of the traditional fault recorder insufficient sampling rate , the accuracy is not high variety of issues have been incompetent current power system fault needs. Meanwhile, the introduction of new technology although the performance of the disturbance recorder has been greatly improved, but also brought a poor stability and lack of reasonable configuration and many other issues . Therefore, the introduction of new technologies in order to ensure the overall performance of fault recorder under the premise of increasing the stability of the device and configure the reasonableness of such issues is particularly important. In this paper, the lack of traditional fault recording technology , according to the power system fault analysis on failure data collection needs, build FPGA as the core of the new design of a portable disturbance recorder . FPGA as the core of the system , through the data acquisition circuit , human-computer interaction and communication circuits extended to achieve a high-speed high-precision data acquisition and transmission failure . This article by calling DSP Builder tool built inside the FPGA digital signal processing module , the realization of fault data digital filtering and fast Fourier transform , enabling the frequency domain analysis of fault data . Meanwhile, the digital signal processing module also completed a start criterion algorithm to protect the device starts reliability. By using SOPC technology , built inside the FPGA NIOS Ⅱ soft-core processor and runs on NIOS Ⅱ soft core μC/OS- Ⅱ operating system , enabling the system task scheduling . Through simulation and actual test , the system is able to complete the fault signal acquisition and storage functions, applicable to the new situation, the power system fault signal wave recording tasks.

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CLC: > Industrial Technology > Electrotechnical > Electrical measurement techniques and instruments > Frequency, waveform parameter measurement and instrumentation
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