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Digital channelized receiver system design and hardware implementation

Author: LiYingXi
Tutor: HeZiShu
School: University of Electronic Science and Technology
Course: Signal and Information Processing
Keywords: Software Defined Radio Digital channelized receiver AD6654 FPGA DSP
CLC: TN851
Type: Master's thesis
Year: 2007
Downloads: 664
Quote: 2
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Abstract


Modern electronic battlefield electromagnetic environment has become increasingly complex and changing the direction of development of the electronic reconnaissance receiver , broadband, digital, software , high interception rate requirements of electronic surveillance equipment , digital channelized receiver . This paper in order to be better able to adapt to the needs of the information battlefield problem of the communications surveillance closing in modern electronic warfare , based on the theory of software-defined radio , a practical digital channelized reconnaissance receiver implementations , designed and implemented a flexible , standard , modular hardware platform , the hardware platform through software programming to intercept the signal of multi- species communication . The advantage of the program can handle multiple signals at the same time , real-time , high probability of intercept , software , a flexible , general-purpose and can be an effective solution to channel analog channel receiver is not balanced . This article on digital channelized receiver technology based on software radio theory , including the basic theory of AD, DDC , multi-rate signal processing theory , the theory of polyphase filter bank , derivation of a polyphase filter bank channelized receiver mathematical model . The background combined project reconnaissance receiver and system requirements , proposed a complete , viable system solutions , including data flow analysis , algorithm design , consider the program on a multi - mode dynamic configuration the polyphase filter multiphase factor and subchannel bandwidth can be dynamically transformation , so that the system can adapt to the ever-changing , passive reconnaissance receiver requirements . In considering costs , on the basis of volume and versatility , the proposed hardware solutions of the system of multi-channel , three-channel analog signal receiving and processing in a single board , reducing the size and cost of the switchboard ; CPCI chassis board interconnect the CPCI bus specification of the use of enhanced versatility . Analysis system demand for the device , complete device selection, the main use of the device : AD6654 , FPGA: EP1S30 , DSP : TS201 . Completed the hardware design and testing . The completed code design and hardware functional verification of FPGA functional modules function debug AD6654 . Proven hardware platform can be completed to meet the system requirements of the reconnaissance receiver .

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CLC: > Industrial Technology > Radio electronics, telecommunications technology > Radio equipment,telecommunications equipment > Receiver equipment, radio Radio > Receiver: the form of points
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