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Based image acquisition and processing system in the FPGA design

Author: ChenLiuHua
Tutor: XuXiaoPing
School: Kunming University of Science and Technology
Course: Control Theory and Control Engineering
Keywords: Image Collection Image Prossesing SOPC FPGA NiosⅡ
CLC: TP391.41
Type: Master's thesis
Year: 2010
Downloads: 176
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Abstract


With the scientific and technological progress and the accumulation of the social wealth, video monitoring systems are walking into all areas of social production and lifes step by step. The rapid development of microelectronics and the maturity of computer image processing technology offer new ideas and options to the designing of the video monitoring system. Video monitoring system can be divided into functional image data collection port, data transmission port and monitoring port from the function. As an important part of the video surveillance system,the design quality of the Image collection system directly affects the speed and accuracy of the whole system and therefore gets more and more attention.In this paper, we design a real-time system based on programmable logic device to implement image data collection and image processing. A new attempt is prevented in our paper to achieve the concept that using SOPC technology and the concept of hardware and software co-design and using the program of FPGA-based embedded chip. The system collects the local image data through the CMOS image sensor and converted into standard industrial resolution 640* 480 RGB format data,then process JPEG compression to reduce the amount of data to transfer data to the monitoring port easily.At last decode the data into RGB data for VGA display in the monitoring port. The image collection and processing system is composed a real-time network video monitoring system with data transmission module and display module.The specific design features are as follows:The system design image collection and processing system with embedded chips FPGA replacing traditional PC, the design core for the control. We use digital data stream from collection to processing to make data transfer and more image processing easy.In addition, we reduce the cost, power consumption and size,and has also greatly enhance on functional expansion and upgrading of hardware flexibility.In order to meet the real time of the image data processing,we use the way of co-design of hardware and software to design the system.We using Verilog hardware describing language to finish the design of image collection and image cache with the advantage of parallel processing by hardware.And the complex JPEG codec algorithm was designed in the Nios soft core using the software. The system was designed based on SOPC technology to ensure that the data are transfer smoothly from the hardware to bus to Nios soft core. In addition, the system also uses rich peripherals and interfaces of the DE2-70 platform, through the joining of SD card to make the data storage.The system compose the image collection and the image cache module to a custom SOPC IP core with writing bus interface,combining with rich peripheral interfaces IP and standard components to save the development time and efficiency of the bottom greatly and realize the function design of the system. The designing custom IP core is relatively independent and can be reused.The design and implementation of the image collection and processing system of the issue has the functions of reference for further expansion of video surveillance system.

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CLC: > Industrial Technology > Automation technology,computer technology > Computing technology,computer technology > Computer applications > Information processing (information processing) > Pattern Recognition and devices > Image recognition device
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