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Research on Switching Architectures Based on Multi-hop Routing

Author: ZhengDeRen
Tutor: WangBinQiang
School: PLA Information Engineering University
Course: Communication and Information System
Keywords: Multi-port output Switching Architecture Scheduling Round Robin
CLC: TN915.02
Type: Master's thesis
Year: 2009
Downloads: 10
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Abstract


Conventional routing and switching technology is designed mainly based on the single forwarding path, giving only one output port to the packets entered the switching device. The contention of packets with the same output port is congestion-proneness, and deteriorating the performance of switching device or even the whole network. So traditional switching scheme has greatly restricted the performance of network.Multi-hop routing mechanism has achieved great development recently, which leads the cells have multiple output ports. So with the new switching scheme study, the scheduling congestion of the same output port can be highly reduced. Based on the researching result of multi-hop routing, the dissertation presents a queues’length dynamic balancing algorithm and a new switching fabric. Combined with the project“A Dynamic Balancing Routing and Switching Mechanism Based on Multi-Hop”supported by the National Program 863, it also gives a project implement scheme supporting multiple output ports.Its main work is outlined as follows:? With the idea of routing and switching cooperating design, the dissertation proposes a multi-port output switching mechanism, then comes to a conclusion that the switching performance improves greatly when the number of arriving cell’s output port is been set to 3, finally validates the conclusion with the Expand Switching Performance Evaluation System.? Combined with the characteristic of the Input queued switch, the dissertation presents a queues’length dynamic balancing matching algorithm. The algorithm balances the queues both by input scheme and by scheduling policy. The simulation results show that the throughput can be increased more than 25% compared to iSLIP under non-uniform traffics with one iteration, and the performance of delay is also improved greatly.? The dissertation builds a switch with parallel memory scheme(PMS). With the flow model techniques we prove that the PMS can achieve a throughput of 100% without speedup. Based on the PMS, we present a parallel distributed compensating round robin algorithm supporting multiple output ports. The algorithm can schedule the queues of different output port independently with parallel flow manner. The simulation results indicate that the PMS switch with PDCRR algorithm can obtain better performance.? According to the requirements of the project and considering systematic performance and implement difficulty, a system solution has been provided based on the PMS and PDCRR. Simulation of FPGA shows that the scheme completely meets the project requirements.

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CLC: > Industrial Technology > Radio electronics, telecommunications technology > Communicate > Communication network > General issues > Communication network structure and design
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