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Design and Validation of SpaceWire Routing IP Core

Author: WeiZuoQian
Tutor: LiHuiJun
School: Graduate School, Chinese Academy of Sciences
Course: Applied Computer Technology
Keywords: SpaceWire FPGA Routing function Verification
CLC: TN47
Type: Master's thesis
Year: 2011
Downloads: 55
Quote: 0
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Abstract


With the development of the technology of space exploration , satellite carrying a payload of more and more . This needs a large number of data communication and data exchange , inevitable requirement inside the satellite communication has a higher processing speed , reliability , resistance to radiation , as well as error detection and error recovery capability . Connect together the various payload the spaceborne data bus plays a key role in the overall system . Spaceborne data transmission network reliability , speed and flexibility of direct impact on the overall performance of the spaceborne electronic systems . SpaceWire is a serial proposed by the European Space Agency in 2003 , high-speed , point-to-point , full-duplex data network standard . Fully consider the characteristics of the space applications to meet the needs of modern spaceborne high-speed transmission of data between devices . Currently , SpaceWire technology has been more emphasis on organizations such as ESA, NASA and JAXA conducted a lot of research in this standard , and the SpaceWire technology has been successfully applied to multiple space missions . The subject in the self-developed SpaceWire Codec IP core based on the the SpaceWire routing IP core design and verification . The the the SpaceWire routing IP core design part is realized through Verilog programming , verify that the part is achieved through the ModelSim software simulation and hardware validation . Which hardware verification , including the two parts of the production SpaceWire PCI board and developed the corresponding software interface . The software interface can be achieved through the PCI bus of the the SpaceWire routing table configuration , data exchange as well as SpaceWire link configuration and status tracking . The final design is verified by simulation and hardware verification and correctness . This paper includes the following contents : the SpaceWire protocol , routing protocols and IP core introduction ; 2 . Of the SpaceWire technology abroad and detailed research situation ; 3 . The SpaceWire routing IP core overall design and sub- module of the detailed design situation ; 4 the SpaceWire routing IP core simulation ; 5 . production hardware , design software interface SpaceWire routing IP core hardware verification .

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