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Mass - Storage SOC chip research and implementation of integrated system

Author: LouXiangXiong
Tutor: DengXianCan；ZhuDaZhong
School: Zhejiang University
Course: Microelectronics and Solid State Electronics
Keywords: SOC Mass-Storage SD card hardware/software co-design
CLC: TN402
Type: PhD thesis
Year: 2004
Downloads: 305
Quote: 3
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Abstract


The design technique of Mass-Storage SOC controller and its principle, function and architecture are discussed in this dissertation. The contributions of this work are summarized as follows:1. By using hardware/software co-design platform-based SOC design method, a Mass-Storage memory controller SOC design platform is built. Thus, hardware and software development can work in a concurrent, co-design, co-simulation and co-verification way on this design platform, this helps to optimize the performance of this SOC chip and reduces the time-to-market.2. A firmware downloadable high-speed architecture of RISC CPU IP core has been designed. The instruction executing speed of this RISC CPU is 4 times fast than classical PIC MCU. Firmware update is supported in this CPU core, too.3. Reed-Solomon and BCH error control coding algorithms have been studied in this thesis. The CODEC circuits are realized by using low-cost and high-speed hardware. Both of the algorithms have been applicated for Chinese Invention Patents.4. The Secure Digital memory card interface IP module is built by using hierarchy design method. The SD interface circuit is implemented by dividing the functions into two individual layers ?physical layer and data link layer.5. A FLASH Direct Memory Access(DMA) technique has been adopt for high-speed data transport between FLASH memory and data buffer.6. The know-how to firmware of Mass-Storage controller SOC chip is discussed in detail. The boot ROM programming and firmware simulation technique are also described.7. In this dissertation, we also finished the testbench generation for manufacture testing. The testbench meets the design rule of Faraday Technology Corporation, and passed on-wafer and package testing procedure at UMC foundry.8. The Mass-Storage SOC chip is manufactured in UMC’s 0.25-micron CMOS process, the gates of this chip around 290,000. From the test results, we observed that the performance of this Mass-Storage SOC chip is comparable to similar international productions or even surpassing. It is a competitive production that has efficient ECC algorithms, high data transport speed and low cost.

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CLC: > Industrial Technology > Radio electronics, telecommunications technology > Microelectronics, integrated circuit (IC) > General issues > Design
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