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Research and design of ESD protection technology of CMOS integrated circuits

Author: ChenZhiJun
Tutor: LiPing
School: University of Electronic Science and Technology
Course: Microelectronics and Solid State Electronics
Keywords: ESD TEST Failure Analysis
CLC: TN43
Type: Master's thesis
Year: 2012
Downloads: 101
Quote: 0
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Abstract


ESD(Electrostatic Discharge) is a very common phenomenon in the IC manufacturing process, thus the ESD protection circuit is also an important part of the integrated circuit design, which will directly affects the performance and service life of the IC. With the continuous advancement of semiconductor manufacturing technology, the feature size of is scaling down, and the thickness of the gate oxide is declining which will result in the lower breakdown voltage of the oxide. In addition, the advanced CMOS technology (such as the implementation of LDD and salicide) will also affect the performance of the ESD protection circuits. As a result, the research and design of ESD protection circuits in IC design becomes more and more urgent and important.The main contents of the paper include the following aspects:(1) Research of the theory about ESD. It analyses the cause of ESD and its harm to the IC, and studies the failure modes of ESD,four Discharge Model of ESD and ESD testing method.(2) Design of the ESD protection circuits. Firstly it studies the physical characteristics of the commonly used ESD protection devices (diode, MOSFET, SCR and resistor), because the design of the ESD protection circuits mainly use the Ⅰ-Ⅴ characteristics curve.This paper is to propose a ESD protection circuit to the OTP memory chip. According to the ESD current path, it proposes the low-impedance current loop to shunt the ESD current. Besides, it design the ESD protection block of the chip.(3) Design of the whole chip’s layout and ESD protection network. LDD and salicide process can improve the standard CMOS device’s performance while in contrast it becomes the disadvantage in the ESD protection device. Finally, it designs the ESD protection network of the whole chip. And it successfully taped out in the0.18μ m process.(4)ESD test of the chip. There are many failure analysis criteria for ESD protection circuit. And in this thesis, when IV curve shift over±30%at the current1μA, its ESD protection is failure. Commissioning relevant agencies, the ESD testing experiments results shows that the chip in this paper meet the design specifications, and the voltage protection level is up to2KV.

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CLC: > Industrial Technology > Radio electronics, telecommunications technology > Microelectronics, integrated circuit (IC) > Semiconductor integrated circuits ( solid state circuits )
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