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A Study of Ultra Low Power Passive UHF Radio Frequency Identification Chip Architecture

Author: TangLongFei
Tutor: ZhuangZuoZuo
School: Xi'an University of Electronic Science and Technology
Course: Microelectronics and Solid State Electronics
Keywords: UHF RFID Tag Chip Backscatter Link Frequency Analog PIE Decoding Analog BLF generator Link Time T1
CLC: TP391.44
Type: PhD thesis
Year: 2012
Downloads: 46
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Radio frequency identification is one of the key technologies for the internet ofthings, which realizes non-contact identification. The RFID system operating in theultra high frequency band has many advantages over systems in other bands. Theadvantages include faster reading speed, longer operation range, able to identify highspeed motion objects, and so on.In this dissertation, through analyzing the ISO/IEC18000-6C standard on passiveUHF RFID and researching on the UHF RFID system and chip, two high performancepassive UHF RFID architectures are realized.Firstly, through study on the UHF RFID architecture in accordance with theISO/IEC18000-6C standard, the critical limitation of the performance is found out. Thebackscatter link frequency (BLF) requires a high precise on chip clock generatingcircuit, which not only leads to high power consumption but also increases the designdifficulty. Thus an improved BLF generation method employing integer and half-integerfrequency divider is developed in this work. By means of utilizing such a divider, in aparticular frequency interval, the BLF value at the center frequency can be used torepresent all other BLF values in that interval. And this can produce the BLF complyingwith the standard. Hence, the clock frequency can be extended from a certain1.92MHzto1.2MHz~5MHz, which greatly reduces the precision requirement of the on chipclock.Secondly, a new UHF RFID architecture based on the analog decoder circuit isproposed. An analog PIE decoder which can decrease the power consumptiondramatically is employed to replace a traditional decoder with the1.92MHz clock.Besides, an analog BLF generator including an integrator-controlled relaxationoscillator is presented in this dissertation. And it’s been verified that the generated BLFfrequency is fully conforming to the ISO/IEC1800-6C standard. Furthermore, anexcellent solution to the difficulty of the T1link time control is invented. It utilizes twointegrators and a comparator to produce a signal used to control the output of the BLFcircuit.Thirdly, a new reference circuit with small area and low power consumption isintroduced, as well as a new demodulation circuit which leads to an area reduce about50%by eliminating the use of passive components. Finally, two kinds of UHF RFID chips with different architectures have beenfabricated under TSMC0.18um RF process. The test result shows both of the two sortsof chips can operate properly. The maximum read range of the chips using the BLFinterval method is7meters and that of the chips using the analog BLF generator is8meters.

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CLC: > Industrial Technology > Automation technology,computer technology > Computing technology,computer technology > Computer applications > Information processing (information processing) > Pattern Recognition and devices > Optical pattern recognition devices
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