Dissertation > Excellent graduate degree dissertation topics show

To research and design of pipelined analog to digital converter circuit sampling

Author: SuYingPing
Tutor: YuQi
School: University of Electronic Science and Technology
Course: Microelectronics and Solid State Electronics
Keywords: SHA-Less pipeline ADC MDAC
CLC: TN792
Type: Master's thesis
Year: 2012
Downloads: 23
Quote: 0
Read: Download Dissertation

Abstract


With the explosive growth of wireless communication systems and portable video device, the demand for low-power and high-speed integrated circuits is indispensable. The analog-digital converter (ADC) is a critical component in these applications, such as filter, video data link, and transceiver. In order to meet demand, the ADC must increase their sampling rate and reduce power dissipation.Among many types of CMOS ADC architectures, a pipelined architecture can achieve good high input frequency dynamic performance. The aim of this thesis is to investigate optimizing ADC specification and the targeted architecture is a SHA-less10bit100Ms/s pipelined analog to digital converter. Normally, pipeline ADC use a front sample and hold circuit to sample the signal and hold forward the next stage. But this structure needs a crucial amplifier which will increase the area and power dissipation.We use Matlab-Simulink to simulate the traditional pipeline ADC, through which we can understand the whole process. There are two structure options for SHA-less ADC. Comparing the two optional modes, we can finally decide which one we can adopt. The pipelined ADC consists of blocks like2.5bit MDAC without front sample and hold stage,1.5bit/stage sub-ADC, digital encoder, digital error correction logic circuit and clock generator.The circuit is designed with power supply3.3V0.35μm CMOS process. The input voltage of ADC is1.3V～2.3V. According to Hspice simulation result, the designed pipelined ADC can operate at100MHz. The Signal-Noise and Distortion Ratio is61dB when the input frequency is10.08MHz and effective number of bit is8.3bit. The power dissipation is230mW.

Related Dissertations

  1. Research on Key Circuits of High Performance Pipelined ADC,TN792
  2. A 60msample/s, 10bit Pipeline ADC in Standard Digital CMOS Process,TN792
  3. 10-bit 50-MS / s low-power pipelined ADC design,TN792
  4. 9 Bit 10MS/s Low Power Pipeline ADC Design,TN792
  5. Research and Design of 12bit High-speed and High-resolution ADC,TN792
  6. Research and Design of Sub-ADC Based on Pipeline ADC,TN792
  7. Design and Implementation of Truly Random Number Generator Based on Pipeline ADC,TN792
  8. Pipelined ADC Modeling and digital calibration algorithm behavioral,TN792
  9. MDAC module 3G receiver with ADC,TN929.5
  10. Research and Design on Pipeline Analog-to-Digital Converter,TN792
  11. The Research of MDAC in High Performance Pipeline ADC,TN792
  12. Design and Realization of 12Bit 100MS/s Pipelined ADCs,TN792
  13. Design of Low-Jitter Clock Duty Cycle Stabilizer for High-Speed A/D Converter,TN792
  14. Sample-and-Hold and MDAC Circuits for Pipeline ADC,TN792
  15. Pipelined A / D converter the offline digital calibration algorithm,TN792
  16. Based on 0.18μm RF-CMOS process 8 100MSPS pipelined ADC MDAC unit , ,,TN792
  17. Design of 12bit 50MSPS PIPELINE ADC,TN792
  18. Research and Design of a 10bit 50MSPs Pipeline ADC,TN792
  19. Research and realization of low power MDAC OTA unit circuit,TN792
  20. Research and Design of MDAC Based on Pipeline ADC,TN792
  21. Design and Implementation of a 12bits 100MSPS Pipeline ADC,TN792

CLC: > Industrial Technology > Radio electronics, telecommunications technology > Basic electronic circuits > Digital circuits > Digital-analog , digital to analog conversion circuit
© 2012 www.DissertationTopic.Net  Mobile