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FPGA simulation of channelized digital receiver

Author: LiuZuoYi
Tutor: LvYouXin
School: University of Electronic Science and Technology
Course: Signal and Information Processing
Keywords: channelized receiver polyphase filter parallel architecture IFM signalreconstruction FPGA
CLC: TN851
Type: Master's thesis
Year: 2012
Downloads: 50
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Abstract


With the development of the technology on radar, a digital channelized receiver includes wide band frequency coverage, simultaneous signal detection, high sensitivity and dynamic range and so on. And the ideal software radio is to place the A/D close to the antenna as far as possible. But at the same time, the digital receiver has the bottleneck problem between the low speed of digital signal processing and the high speed A/D processing ability. A digital channelized receiver provides most of these requirements, so it is widely used in the modern electronic warfare application.A digital channelized receiver can obviously reduce the requirement of corresponding hardware and improve the real-time processing ability. So the thesis is working on the technology of a digital channelized receiver. The main content is summarized as follows:1. The technology of a digital channelized receiver is firstly discussed. Then aimed at the non-maximum decimation of filter bank channels application, a channelized receiver based on polyphase filter banks is deduced and solved the requirements of data processing and the total probability;2. The digital channelized receiver based on parallel architecture, which is used the relationship between the number of the channels and the decimation, is proposed to improve the data throughput and real-time processing ability;3. To cover the entire bandwidth with no blind spots between the channels, two methods about overlapping channel division is applied to ensure the total probability. And the Instantaneous Frequency Measurement(IFM) is used to arbitrate the signal truly belongs to which sub-channel. The related simulations verify the effectiveness and feasibility;4. Modified Discrete Fourier Transform(DFT) filter banks is applied with almost perfect reconstruction(PR). The results by Matlab show the correction and feasibility;5. The design of the digital channelized receiver, which instantaneous bandwidth is600MHz, is completed by Matlab and FPGA software program; 6. Finally, the simulation results are given and analysed. The feasibility of the system design is verified.

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