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And implementation of wideband channelized digital receiver based on FPGA

Author: ZhouWei
Tutor: LvYouXin
School: University of Electronic Science and Technology
Course: Signal and Information Processing
Keywords: digital channelized receiver FPGA decimate polyphase filter IFFT
CLC: TN851
Type: Master's thesis
Year: 2012
Downloads: 45
Quote: 0
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In order to overcome all kinds of disadvantages of analog processing, software radio demands the A/D and D/A should be closer to the antenna. With the bandwidth of input instantaneous frequency wider, the sampling rate must be higher. However, in the complicated electronic environment today, not only should the instantaneous processing bandwidth be wide, but the ability of real-time and multi-signal processing should be access. It challenges the speed of digital signal processing of modern receiver. Therefore, the wideband digital channelized receiver is the product complying with the request and has been one of the important research subjects of digital receiver.Based on the basic principles of sampling theory, multi-rate signal processing, polyphase filtering and so on, the structure of digital channlized receiver is discussed and analyzed. In this paper, design of the digital channelized receiver system as well as implementation of key technologies is mainly studied with instantaneous frequency bandwidth750MHz and sampling rate up to1.5GHz. The primary contents are as follows:1. A program of wideband digital channelized receiver is designed in the basis of polyphase DFT structure, and simulation of MATLAB verifies the feasibility of the design.2. According to the system design, implementation of various modules is accomplished in the FPGA including decimation, polyphase filtering, parallel IFFT and synchronous clock management. In this design, on one hand, hard-cores are used to design modules of decimation and clock management, on the other hand, combining practical request, optimized implementation of polyphase filtering and IFFT is designed in the terms of speed and resource utilization.3. Upon the system design indicators, appropriate chips are chosen. In order to build the hardware platform, the overall design of schematic circuit diagram and printed circuit board are completed by Cadence based on ADC and FPGA.4. On the hardware platform, software and hardware tests are debugged to confirm the effectiveness of the mentioned design and also indicate that the wideband digital channelized receiver can be applied to the practical application well.

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CLC: > Industrial Technology > Radio electronics, telecommunications technology > Radio equipment,telecommunications equipment > Receiver equipment, radio Radio > Receiver: the form of points
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