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The Design and Implementation of a Baseband Digital Receiving Module for MODIS Based on MSP430and FPGA

Author: HanZuo
Tutor: YeMing; ZongPeng
School: Nanjing University of Aeronautics and Astronautics
Course: Communication and Information System
Keywords: MODIS data baseband digital receiver QPSK digital demodulation R-S decoding MSP430microcontroller FPGA
CLC: TN911.7
Type: Master's thesis
Year: 2012
Downloads: 36
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Abstract


TERRA and AQUA are two major satellites in EOS (Earth Observing System) of USA. AndMODIS is an important sensor deployed on the TERRA and AQUA satellites. The satellite equipmentcan broadcast real-time Earth observation data to the world through X-band, and the low graphic datacan be received for free. Products of MODIS data are very important for the applications of weather,agriculture, military and Earth Observation etc. Currently, the domestic manufacturers and someinstitutes are engaging in research, technical preparation, pre-development of the EOS receivingsystem. An imported system from abroad is very expensive. Therefore, self-developed MODIS datareceiving system is very essential. In light of it, this paper presents a baseband digital receiver forMODIS based on MSP430and FPGA. It can recover the original MODIS data through the basebanddemodulation and decoding technology.The main outputs and contributions of this work are as follows:1. According to the MODIS data formats and the signal processing on the satellite transmitter, wepropose a receiving program for MODIS combined with knowledge of satellite communicationsystems. The structure of the receiving system is described especially on the design of basebanddigital receiveing module.2. The principle of the baseband digital receiver technology, such as analog-digital conversion,QPSK digital demodulation, R-S code, packet interleaving, convolutional encoding and decoding aredescribed in this report. In order to design the baseband digital receiveing module, we develop areal-time baseband receiver hardware circuit by using STMicroelectronics’s digital demodulation anddecoder chip STV0299B and Xilinx’s FPGA chip XC3S2000.3. Implementing digital demodulation functions viaI2C bus technology, using a MSP430F169microcontroller to control a STV0299B demodulation chip.4. Implementing frame synchronization, de-interleaving device, R-S decoder design modules inFPGA module. In order to improve the coding efficiency we design the R-S decoding algorithm byusing the pipelining mechanism.5. Designning the hardware and software of the baseband digital receiveing module for MODISand setting up a test platform by using the MATLAB.In the project, the correctness of the module design is verified through software simulationrunning on the FPGA module and the test platform in PC, the module is tested by using MODIS data formats in pretreatment methods. According to the simulation results and analysis of bit error rate inMATLAB simulation tool, the baseband digital receiveing module for MODIS works perfectly andmeets the requirements.

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