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Research and Design of an All Digital Phase-locked Loop Based on Adaptive and PI Control

Author: JiangXiaoJun
Tutor: DanChangHong
School: Nanhua University
Course: Physical Electronics
Keywords: Proportion-integral (PI) Control Adaptive Control All Digital Phase-Locked Loop (ADPLL) VHDL FPGA
CLC: TN911.8
Type: Master's thesis
Year: 2013
Downloads: 8
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Abstract


Phase-locked loop(PLL) is a negative feedback control system that can effectively track input signal’s phase. Phase-locked loop(PLL) is widely used in the field of communication, radio electronics,automatic control and power system, it has been a very important component in all kinds of electronic systems. Analog phase-locked loop has some characteristics such as:nonlinear of voltage-controlled oscillator (VCO),the phase detector (PD) is inaccurate, components are easily saturated,and high-order phase-locked loop is unstable. All digital phase-locked loop (ADPLL) can eliminate those defects which are exist in Analog phase-locked loop(PLL),but also has advantages of parameter stability, high reliability and easy integration.Therefore,ADPLL is having been more and more applied.In this paper, based on in-depth study of the theory and structure of various types of phase-locked loop(PLL), the control law of all digital phase-locked loop (ADPLL) based on proportional-integral(PI) control is researched,and its steady-state performance and dynamic performance are analysed by using Matlab software.Then, to solve the problems of a narrow lock frequency range, the loop control parameters and the free oscillation frequency can not be regulated online exist in previous systems, all digital phase-locked loop based on the adaptive and PI control is proposed. When the input signal frequency changes within a small range, the all digital phase-locked loop (ADPLL) dynamically adjusts the loop parameters in accordance with the size of the phase error, to achieve lock on the input signal phase. When the input signal changes in a larger frequency range, the adaptive controller can automatically adjusts the proportional integral parameter and the free oscillation frequency of the loop according to the input signal frequency changes, to achieve fast track in loop, not only improve the phase-locked speed, but also expanded the phase-locked range. Finally, in Quartus II software environment, the entire all digital phase-locked loop circuit structure is devised by VHDL as well as making use of Top-Down and modular design method,and evaluated based on simulations, the function of the all digital phase-locked loop system under different control parameters are compared and analysed, and evaluated with Field Programmable Gate Array (FPGA) based on experiments.System simulations and experimental results show that Phase-locked loop implemented by adopting composite control of proportional integral control and adaptive control can real-time regulate loop control parameters and free oscillation frequency with the input signal frequency changes. When the system clock is1.25MHz, the longest time for the loop arriving its locked state is less then8cycles of the input signal, the Frequency lock range is1.25-5kHz, In addition, it has characteristic of its simple structure and easy system integration.

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CLC: > Industrial Technology > Radio electronics, telecommunications technology > Communicate > Communication theory > Phase lock, the lock-in technique
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