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H.264Video Coding SOPC Design Based on FPGA

Author: LiXingYuan
Tutor: HouYiBin; WangSuYu
School: Beijing University of Technology
Course: Computer Science and Technology
Keywords: H.264 FPGA software coding system double precise floating point unit intra-frame encoding loop
CLC: TN919.81
Type: Master's thesis
Year: 2013
Downloads: 2
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Abstract


In recent years, the widerspread of smart mobile terminals and the nextgeneration mobile networks provide a broad space for video applications. But,compare to the growing demand for video services, network resources are extremelylimited. Therefore, academia and industry invested a lot of energy in research ofefficient video compression technology, and the H.264video coding standard is oneof those results. Adopting a serial of advanced coding techniques, H.264greatlyexceeds the coding performance of all previous standards and has better adaptabilityof networks and robustness. Consequently, H.264win a lot of attention oncepulished, but the excellent encoding performance of H.264was reached at a cost ofdramatically increased of computation, how to implement the H.264encoderefficiently and economically becomes a key issue of H.264application.For the sequential processing architecture of traditional general-purpose CPUand DSP can not meet the demand for high-resolution, real-time encoding, using adedicated hardware H.264encoder has become inevitable. SOPC contains thecharacteristics of both SOC and FPGA. With high efficiency and low cost, SOPChas become the research hotspot of implement a H.264encoding system.Firstly, this paper begins research of H.264coding algorithm and architecturecharacteristics from the H.264standrd. Then, according to the analysis results, thispaper further research the SOPC implementation of H.264video coding system,which including softerware and hardware division, interface and cooperation design.Subsequently, by transplanting the PC based X.264open source encoder and aappropriate file transfer program, the software section of video encoding SOPC isfinished. In order to improve the performance of system central controller RISCMicroBlaze soft-core and to seed up the double precision floating point operations inX.264, this paper designs a MicroBlaze double precision floating point unit. Byadding the unit drives to the compiler automatically calls floating point libraries, theunit is tightly coupled to the MicroBlaze. Test results show that the extendedMicroBlaze largely reduce the double precision floating point algorithm executiontime. Finally, according to the characteristic of macroblock level H.264encodingalgorithm, this paper designs a H.264hardware encoder IP core and implement thehigh computational and data correlated intra coding loop, which contains full mode parallel perdiction and selection models,16pixels parallel transform, quantization,IT, IQ and reconstruction models. Simulation results show that the parallel intracoding architecture and each function modules proposed in this paper can greatlyimprove the execution speed of related algorithm; a part of those modules take lessresource consumption and the overall loop performance is better than existingrelated works; the encoding loop have ability to meet the high-definition real-timeencoding.

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CLC: > Industrial Technology > Radio electronics, telecommunications technology > Communicate > Image communication, multimedia communication > Image coding
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