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The Research of Efficient Wide Convergence Scaling-free CORDIC Algorithm and Architecture

Author: LiuMing
Tutor: RenXiaoXi; ChengXiaoNan
School: Hunan University
Course: Electronics and Communication Engineering
Keywords: CORDIC algorithm Parallel and Digit-drop iteration GlobalConvergence Angle Correction FPGA
CLC: TP301.6
Type: Master's thesis
Year: 2012
Downloads: 10
Quote: 0
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Abstract


The rapid development of information technology has led to a large number of complicated data which need high precision, low delay and low consumption. The traditional method of data processing is facing a big challenge, but the CORDIC (Coordinate Rotational Digital Computer) algorithm can convert complex matrix, transcendental function, digital signal processing function into a simple operation of shift and addition/subtraction.it not only can greatly accelerate the data processing and reduce the hardware resources, but also can be implemented easily on hardware.In this research, we pay more attention on analyzing the SF(Scaling-Free) CORDIC algorithm. When we analyze the performance of this algorithm and its improved version on precision, time delay and hardware resource, we find that existing SF CORDIC have some drawbacks like smaller convergence range, higher delay and larger area. Therefore, in this research we propose two new methods to improve the performance of algorithm:Firstly, we propose a method of new global convergence. We increase the convergence, and then, we extend it to the whole quadrant through new domain unfolding technology which can make the algorithm convergence wide enough to all angles. We introduce a method of angle correcting to adjust iteration error which comes from the iteration of angle out of original convergence. We analyze precision, delay and hardware resource.Secondly, we propose a method of partial parallel and digit-drop iteration. We simplify further the iteration formula of second half part to which we can implement it parallelly. We drop some digit of operand which take part in shifter and adder/subtractor and implement parallelly addition through three-in adder. We analyze precision, delay and hardware resource.Finally, we optimize a part of the architecture of our algorithm to achieve a better performance. We realize our proposed method and its architecture on FPGA. The outcome shows that our proposed method have a better performance which means we get a smaller delay and less hardware resource consumption without decreasing of precision.

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CLC: > Industrial Technology > Automation technology,computer technology > Computing technology,computer technology > General issues > Theories, methods > Algorithm Theory
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