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Research on the Related Technologies of Network Processor and Its Processing Unit

Author: MaJinFeng
Tutor: JiZhenZhou
School: Harbin Institute of Technology
Course: Computer System Architecture
Keywords: Network Processor Network on Chip Processing Unit coprocessor route lookup
CLC: TP393.05
Type: Master's thesis
Year: 2011
Downloads: 13
Quote: 0
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Abstract


With the rapid development of communications technology, today’s internet is developing to the next generation network including Massive data transmission, voice and video and other high-bandwidth services. This development puts forward new requirements for the packet processing capacity and speed of the network infrastructure overall, the traditional network data transmission solutions based on ASIC and general-purpose processors can no longer meet the needs of the speed and flexibility of packet processing. So programmable network processors, based on specific instruction set processor technology, specifically for high-speed network data processing tasks is coming.This paper introduces the architecture of modern network processors first. And then analyzes two common problems faced by current network processor design. One is lack of instruction-level parallelism, and the other is the topology of processing unit is not flexible enough. On this basis, an architecture of the network processor based on the network on chip technology and the very long instruction word processor structure is proposed in this paper. The architecture can solve the above two problems. Very long instruction word processing unit can increase the instruction-level parallelism. The Network on Chip‘s can carry load balancing automatically and the algorithm of dynamic mapping processing resources to each network segment processing tasks proposed in this paper make the network processing unit topology have a relatively strong flexibility.Second, this paper studies the design of the structure of very long instruction word processing unit, and designs the coprocessor communication interface and some special instructions according to the characteristics of the network processing tasks using hardware mechanisms. Besides, the simulation is also given to prove the correctness of the design.At last, this paper studies the coprocessor related technologies corresponding to the designed route lookup instruction in-depth specially, and propose a tree bitmap routing lookup algorithm which is easily implemented in hardware, based on variable-branch Trie structure. The routing table lookup algorithm’s performance and suitability of the hardware are also analyzed; the result shows that the performance of the algorithm and hardware implementations can achieve the requirements.

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