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Scalable matrix calculation DSP (FT-Matrix) with its unique format , including instruction set , register set , including a new architectural features . Therefore , in order to be able to run on the operating system and other software, you must have the appropriate connector assembler to translate source code from a compiled binary executable file to convert . Assembler and the connector was developed chip development work is an important component. In this paper, FT-Matrix including VLIW instruction packet format , DSP addressing modes , registers, functional units , and many other resources, and different from other DSP features , especially in the assembler , the mixed output for variable-length instructions and macro assembler extensions and other special requirements , do a detailed analysis and research , through to COFF file format , BFD library , assembler and linker -depth understanding of such framework , based on the realization of the FT-Matrix Binutils assembler and connectors. For graphics, image processing and base station applications developed DSP assembler connector requires extensive testing in order to optimize and improved tests in this article , citing two graphic image processing algorithm function , the assembler generated for two functions after three test methods binary validation of assembler connector reaches the basic requirements, test results show that the output is correct , good adaptability .
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