Dissertation > Excellent graduate degree dissertation topics show

The SOPC Implementation of I-CASH Page Compression Subsystem

Author: XiaoZuo
Tutor: HuDiQing
School: Huazhong University of Science and Technology
Course: Computer System Architecture
Keywords: hybrid storage Field Programmable Gate Array Solid State Disk Intelligently Coupled Array of SSD and HDD
CLC: TP333
Type: Master's thesis
Year: 2013
Downloads: 3
Quote: 0
Read: Download Dissertation


SSD (Solid State Disk) storage technology has been developed very quickly recent years, and has some storage market occupancy due to its high performance. However, there is still a great gap between the life span and cost of SSD and those of HDD (Hardware Disk Drive). Therefore, hybrid storage technology which combines both SSD and HDD technology and take advantage of each characteristic appears. By using hybrid storage technology, we can achieve high performance which is close to SSD and long life span and big capacity which are close to HDD.I-CASH (Intelligently Coupled Array of SSD and HDD) is a special parallel structure hybrid storage. I-CASH takes advantage of content locality. It stores reference page data which is not frequently changed in SSD and store the delta data which is frequently changed in HDD. so it can achieve several times performance of HDD. Otherwise, I-CASH reduces write operation in SSD, so the life span of SSD can be extended.This paper introduces the structure of I-CASH, the SOC main control chip implementation. In this implementation, main data computing is operated by specific integrated circuit in chip. Due to the complexity of the whole I-CASH system, this paper only presents the research about the design of I-CASH page compression subsystem and the implementation in FPGA. The structure of compression subsystem and implementation of each module is introduced, especially the core data computing module is introduced in detail. The data compression algorithm and data format stored in HDD is introduced.The design has been validated in FPGA, this I-CASH page compression subsystem can complete page data compression and decompression correctly. By changing different reference page data and writing data, tests under different situation have been done. The speed of operation in data compression and decompression is about150MB/s.

Related Dissertations

  1. Design of Global Clock Distribution and TDC Module Based on FPGA,TN791
  2. Research on Flash-based Hybrid Storage System,TP333
  3. Convolutional code decoding algorithm and its FPGA implementation,TN791
  4. Lightning FPGA-based signal processing research,TN791
  5. PCI-E interface -based data acquisition system FPGA Design and Implementation,TN791
  6. FPGA-based 3G BERT Design and Research,TN929.5
  7. Airborne synthetic aperture radar signal simulation,TN958
  8. π/4-DQPSK baseband communication system design and simulation,TN919.3
  9. Research on Hierarchical Parallel Hybrid Storage System,TP333
  10. Simulation and FPGA Implementation of Wireless Channel Model,TN791
  11. Digital IC tester channel circuit design,TN407
  12. Research and Design of SEU immunity of SRAM -based FPGA test system,TN791
  13. The Implementation of T-MMB Receiver Demodulation Algorithm Based on FPGA,TN791
  14. Research and Design of Architecture and Central Control Module in Multi-standard Video Post Processing Chip,TN402
  15. FPGA Implementation of Digital Down Conversion,TN791
  16. Turbine Set Control System Optmizing,TK263.72
  17. Research and Design of SSL Vision System Based on FPGA,TP242.62
  18. Design and Implementation of the Software & Hardware of a Control Board for the ATM Prototype Switch Onboard,TN915.05
  19. Design and Implementation of Technology Mapping Algorithm in LUT-Based FPGA,TN791
  20. A new FPGA packing algorithm,TN791
  21. The Simulation and Design of the Quasi-cyclic LDPC Decoder in T-MMB Standard,TN764

CLC: > Industrial Technology > Automation technology,computer technology > Computing technology,computer technology > Electronic digital computer (not a continuous role in computer ) > Memory
© 2012 www.DissertationTopic.Net  Mobile