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Research and Implementation of FPGA Real-time Video Image Capture and Display System

Author: GongZhen
Tutor: WuGuanMao
School: Anhui University of Technology
Course: Applied Computer Technology
Keywords: Image acquisition FPGA Decoding and encoding
CLC: TP391.41
Type: Master's thesis
Year: 2013
Downloads: 51
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Abstract


In recent years, with the rapid development of integrated circuit technology, the image processing technology has made great progress on the hardware platform. In the conventional image processing techniques, the general software implementation of image processing algorithms will increase the amount of the data, and it will achieve slowly. For some of the high real-time requirements, the speed of image processing will be demanding. In the real-time image processing system, the key technology is acquisition and processing. The speed and the quality of the image acquisition will affect the performance of the entire system directly. Currently the appropriative image processors mainly include the ASIC, DSP and FPGA. Combined with the advantages and disadvantages of each image processor, and the speed of the image processing, the FPGA programmable logic design is the ideal choice of the target hardware.As the superior performance of the FPGA on the hardware implementation, we designed a FPGA-based real-time video image acquisition and display system. In the hardware,the program using the Altera Cyclone II family of processors as the master chip, using the image decoder chip and encoder chip of Philips, collocating two SRAM and SDRAM as the image storage space, this design can greatly reduce the FPGA logic resource consumption. In the implementation of the hardware, we use the verilog language to build top-level aspects of the schematic design, and use the PLL of the Alter FPGA IP core to control the entire system global clock. Although the FPGA has integrated the hard core of the DSP and general purpose CPU to constitute a programmable on-chip system(SOPC), considering the real-time of the image processing, we abandoned to use the Nios II soft-core processor constituting an image processing system. We use the way of pure hardware to achieve the image acquisition and display system.The system is designed to run in the Altera Corporation quartus ii9.0compiler environment. The experimental results show that using FPGA as the master chip could be have a higher speed than the common chip and the software procession.

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CLC: > Industrial Technology > Automation technology,computer technology > Computing technology,computer technology > Computer applications > Information processing (information processing) > Pattern Recognition and devices > Image recognition device
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