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Design of Speech Coder VLSI Based on AMR Standard

Author: ZhengHaiDong
Tutor: WangJinXiang
School: Harbin Institute of Technology
Course: Microelectronics and Solid State Electronics
Keywords: Speech coding AMR DSP soft core ASIC accelerator FPGA
CLC: TN912.3
Type: Master's thesis
Year: 2009
Downloads: 24
Quote: 0
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Abstract


With the development of modern wireless multimedia communication , and the communication system is limited bandwidth resources , the development of high-quality and low bit rate speech coder become a pressing issue . AMR ( Adaptive Multi-Rate ) speech coder due to its low bit rate and high quality , so widely used in the field of communication and multimedia , at the same time due to the continuous development of the integrated circuit design methodologies and software tools , low-cost, low-power high-performance AMR speech coder has been entirely achievable . Made an in-depth study , the principle of the AMR encoder and algorithms implemented in C and do a detailed simulation and analysis . According to the simulated data , the algorithm characteristics for AMR speech coding standard , the architecture of a \Specific hardware modeling in the design of a good architecture , the encoder algorithms . First, the optimization of DSP soft core , improved soft check the AMR encoding algorithm based on the DSP ; the AMR encoder full compilation realization and optimization of assembly code to test and give the results of data ; based on a compilation of test data , detailed analysis and design of ASIC accelerator ; detailed verification and analysis carried out on the entire design . FPGA prototype verification , to ensure the functional correctness of the design in terms of functionality . Reuse design module ASIC accelerator design , versatility and portability makes the design of G.72x series voice coding algorithm . Design HJTC0.18μm technology library , the operating voltage of 1.8V, the maximum operating frequency of 110MHz . When working at 20MHz frequency to meet the requirements of real - time speech coding 20ms delay , design power consumption of only 20mW , the design area of ??only 150,000 (including on-chip memory ) , the final design in MPW .

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CLC: > Industrial Technology > Radio electronics, telecommunications technology > Communicate > Electro-acoustic technology and speech signal processing > Speech Signal Processing
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