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Research on Digital Multiplexing Technique Based on FPGA

Author: ZhangXiuFeng
Tutor: HuLiaoLin
School: Xi'an University of Technology
Course: Measuring Technology and Instruments
Keywords: Digital Multiplexer Tap FPGA Bit synchronization Frame synchronization
CLC: TN791
Type: Master's thesis
Year: 2009
Downloads: 73
Quote: 0
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Abstract


With the development of modern digital communication technology, the data transfer rate and bandwidth requirements. In order to expand the transmission capacity and to improve the transmission efficiency, in the base-band transmission systems, often based on the time-division multiplex principle, through digital multiplexing with tap (collectively referred to as digital multiplexing techniques) to achieve different rate class data stream combined with the separation, in order to more rational use of high-capacity transmission channel. Digital multiplexing technology is more widely used in the field of optical fiber communications, digital microwave communications and digital program-controlled switching technology. Digital multiplexing technology has formed a common standard and system, the quasi-synchronous digital hierarchy (PDH) and Synchronous Digital Hierarchy (SDH). In the long run, SDH will replace PDH. But because of the high the PDH multiplexing system channel utilization, simple equipment, some small-scale, small-capacity communication network, still with a wide range of markets and applications. Early PDH multiplexing many parts of analog circuits, there are significant limitations. Therefore, to study how to use field-programmable gate array FPGA (Field Programmable Gate Array) PDH multiplexer circuit digitization of great significance. In this paper, digital multiplexing technology theory, design a FPGA-based synchronous digital multiplex system. Its main function is multiplexed end four branches synchronous digital signal together all the way to co-channel signal, in the the tap end this combiner signal back into the original four signals, the system function implemented by the FPGA chip. The full text includes the following main elements: First, the digital communication system, the principle of digital multiplexing and synchronization technology knowledge, to establish a way to achieve the multiplexing / demultiplexing scheme. Secondly, the use of FPGA Quad synchronous digital multiplex system analysis and design, including five modules: HDB3 (High Density Bipolar) encoding / decoding, bit synchronization clock signal extraction, frame synchronization signal extraction, multiplex system and tap system. This paper describes the design of each module ideas, and bit synchronization and frame synchronization circuit performance indicators has been optimized. System design using schematic entry and VHDL hardware description language programming as the way to achieve, and in the the Quartus Ⅱ development and simulation results. Finally, system commissioning, the system is given to download and configuration process, the problems in the design. The design of digital multiplexing system, the internal integration of a number of modules, the main function can be single FPGA chip, and has high scalability and good portability. The results of this design can be used for the Digital Optical chip or system-on-chip design, digital multiplexing design has a certain reference value.

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CLC: > Industrial Technology > Radio electronics, telecommunications technology > Basic electronic circuits > Digital circuits > Logic circuits
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