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High-performance fixed-point YHFT DX DSP instruction control unit Research and Implementation

Author: YangHui
Tutor: SunYongJie
School: National University of Defense Science and Technology
Course: Electronic Science and Technology
Keywords: Digital signal processor (DSP) Long instruction word VLIW Compact instruction set Cross- border payment instructions Zero-order instruction buffer Distributed dual-channel decoder
CLC: TP368.1
Type: Master's thesis
Year: 2009
Downloads: 23
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Abstract

Development of information society, depends largely on the information and signal processing technology advanced. Digital signal processor (DSP) as the core of digital signal processing, which has been extensively applied to aerospace, aviation, radar, sonar, communications, household appliances and other fields, to become the heart of electronic systems. On the promotion of the development of high-performance DSP technology advances in these areas, play an important role. YHFT DX DSP University of Defense Technology is a high-frequency self-designed, high-performance 32-bit fixed-point DSP. Outflows using eight VLIW architecture, compact instruction set, eight feature shared 64 general purpose registers, can simultaneously transmit eight parallel instructions, the length of time to wait parallel instruction from the 16 and 32-bit compressed instruction constitutes a RISC-like instruction , Harvard architecture, two cache, 500MHz frequency, peak computing speed of up to 4000MIPS, has a powerful data processing capability, on-chip integrates a wealth of peripheral resources. This article studies YHFT DX DSP core instruction control and optimization techniques applicable to the completion of the high-frequency section DSP instruction control unit design, verification and synthesis. The main research work includes: an analysis mainstream high-performance DSP core structure; on this article relate to the high-performance technical means, the existing domestic and foreign research are reviewed. 2, system architecture design and analysis. Focuses on YHFT DX DSP instruction system made a thorough research. Enhanced instruction and compression around the directive is implemented to analyze and gives functional division of the pipeline. 3, analysis of the impact of three key factors core performance, combining characteristics of the architecture proposed distribution of the secondary instruction window, an improved method of sorting and distribution of a range of optimization strategy instruction completion of cross-border hybrid distributed and completed No instruction processing unit. 4, analysis of the basic principles and methods decoder, based on three strategies to improve the decoding efficiency, increase the absolute decoding speed, balanced line and extended hardware structure with the system, the design of a distributed two-channel decoder efficiency. 5, the main study the current microprocessor design verification methods and strategies designed to complete the module level, component-level verification. Software co-simulation-based verification strategy and system verification platform to build, complete full-chip functional verification. Gives the synthesis and optimization strategies and results. The results show that instruction control unit designed to fully comply YHFT DX DSP high-frequency, high-performance design requirements.

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