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FPGA-based speech recognition system design and implementation

Author: WangMingJuan
Tutor: HuWeiPing
School: Guangxi Normal University
Course: Circuits and Systems
Keywords: FPGA SOPC Speech Recognition Voice capture FFT IP core
CLC: TN912.34
Type: Master's thesis
Year: 2009
Downloads: 432
Quote: 4
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Abstract


In recent years, speech recognition research largely concentrated in the algorithm design and improvement, etc., and with the rapid development of semiconductor technology, the increasing scale integrated circuits with various levels of R \u0026 D technology continues to improve, the launch of a new hardware platform, Voice Recognition implementation platform have more choices. Voice recognition technology with DSP, FPGA, ASIC and other devices as a platform for embedded systems combined, and gradually to practical miniaturization direction. This issue through a variety of existing speech feature parameters and isolated word speech recognition model based on the research, focusing on exploration algorithm based on dynamic time warping DTW model isolated word speech recognition in the field of application, combined with FPGA-based SOPC system, In the embedded platform with better accuracy and speed isolated word speech recognition system. The overall system design based on the DE2 development platform based on Nios II SOPC technology. The advantage of using this solution is implemented on-chip system, reducing the physical size and overall power consumption; while the system control center are implemented within the FPGA, you can very easily update and upgrade the system, greatly improved the system's general and maintainability. In addition, this system requires a lot of high-speed data operation, in the design of the full use of the rich Cyclone II chip hardware multiplier, to achieve a voice signal endpoint detection module, FFT Fast Fourier Transform module, DCT discrete cosine transform module hardware design module. In order to improve overall system performance, the author takes full advantage of high-speed parallel FPGA advantage, as well as supporting the development environment, the Avalon bus custom hardware peripherals, the system's ability to handle digital signals greatly improved, and its performance is better than the traditional micro-control and the general DSP chip. This thesis includes the following aspects: (1) combined with ALTERA CYCLONE II chip features to determine the FPGA-based speech recognition system design, on the basis of the system hardware and software selection and design. (2) self-designed pure driving circuit hardware description language design, completed the acquisition of high-speed voice work, and on-chip SRAM to store data in the original voice data into MATLAB platform to extract test data is correct. The way the program test module testing the system plays an important role. (3) complete high-speed fixed-point 256-point FFT module design, this module is the system is the key to success, to achieve high-speed real-time computing. (4) combining the characteristics of SOPC design and friendly man-machine interfaces, such as the LCD display prompts the feedback information, etc., and the use of some of ALTERA driver interface provides user-customized system design is completed. (5) for the overall system test, the system can achieve a more stable real time processing object, has a potential market value.

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CLC: > Industrial Technology > Radio electronics, telecommunications technology > Communicate > Electro-acoustic technology and speech signal processing > Speech Signal Processing > Speech Recognition and equipment
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