|
Ethernet is the most widely used LAN, Ethernet for its reliability, simplicity and flexibility still continued development of Ethernet low cost, easy to maintain, occupy the mainstream of the market. Meanwhile, with the development of semiconductor technology, exchange-chip integration is also growing, with the hardware to achieve exchange, data exchange rate is high, can follow the communication protocol and norms, control and communication data management capabilities. This project is mainly to study the Fast Ethernet switching technology, Ethernet switch chip combined with semiconductor technology, solve Ethernet high-speed switching hardware implementation. This paper first introduces Ethernet and Ethernet protocol analysis the current mainstream exchanged chip architecture, master switch chip works, in-depth research to Fast Ethernet certain exchange technologies, including chip switch fabric analysis, research flow control, address learning, spanning tree, virtual LAN technology. This paper presents a study, based on a system of shared memory Ethernet switch chip design, emphatically describes the switch chip module division as well as the main function of each module. After the storage control unit of the switch chip detailed functional analysis, given the specific design of the storage control unit, including data frame cache management, send ports descriptor queue management, the Address table management and traffic control four modules design. This paper presents an efficient and easy hardware implementation of a linked list structure and organization of the idle data space, data cache space allocation and recovery. Descriptor structure, the need to exchange data frames for the stored information of the data frame defined by the address pointer and the data cache space associated send port queue descriptor. Required for high-performance network to provide different services to different levels of traffic of the port during the send port queue scheduling, this article uses a weighted fair queuing algorithm, it would be fair scheduling high-priority and low-priority queue, making traditional applications, users will not be aware of changes in response time and throughput, and those emergency applications, users can also get a timely response. Port address in the Ethernet switching process is essential, this article uses a hashing algorithm to organize the address table, and at the same time address learning, address resolution and address entry aging concrete realization. To prevent data buffer overflow, according to the IEEE802.3 protocol, data frame buffer flow control to achieve. The end of this article describes the RTL-level design of the storage control module method, the soft functional verification platform, the functionality of the switch chip to meet the design requirements, hardware test platform FPGA prototype verification, 8 port switch chip to achieve wire-speed forwarding , frame loss rate, transmission delay, and other indicators of compliance with the relevant standards.
|