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ASIC Design of CMOS SENSOR Interface

Author: LiJianJun
Tutor: LiuPeiLin；ZouWeiYu
School: Shanghai Jiaotong University
Course: Electronics and Communication Engineering
Keywords: AMBA ASIC Scaling down Ping-Pang Buffer Clock Gating Verification Low Power Design
CLC: TN492
Type: Master's thesis
Year: 2008
Downloads: 88
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Abstract


Along with the semiconductor science and technology fast development, the embedded system application with image function is increasingly much more. The present CMOS image sensor are more and more integated into each kind of application, from consumable application products and so on the handset, DSC, toy to industry controls and so on digital video surveillance and guards against the product peacefully, in addition the medical electron and the automobile electron market, image capturing and processing has become one of important constituents. With the VLSI rapidly development at the same time, ASIC design is more and more widespread. So I bring out the ASIC design of CMOS sensor interface.In this paper, this design mainly function is the realization correctly sampling Sensor output image data. First it analysis the different CMOS Sensor output characteristic and needs, based on the two kind of characteristic, or CCIR656 and CCIR601, it proposed with emphasis based on in the ARC600 SOC chip the CMOS image sensor control interface circuit module design: this design hangs on the AHB,so the AMBA is analysised, has considered AHB when arose suddenly visited external memory the address bus to have the 1K Bytes boundary request as well as burst length transmission influence the system, and bring forward the burst length arbitration mechanism,or one time burst transmission to be possible again to divide certain transmissions the method according to needs; Then has reserched the method of data bus transfer between the different clock domain, proposed the gray code way under the asynchronous clock domain data transmission; simultaneity, in order to reduce the system bandwidth usage,here proposed the image scaling down architecture; In order to prevent the loss on data transmission, proposed the ping-pong buffer structure regarding internal data buffer; And has analyzed serial camera control bus; Had considered the chip cost saving and low power design, used the gating clock method to do the logic synthesis; Finally gathers the corresponding image data through the AHB master transfer the data ouput to the external buffer by DMA mode. It provides the video data for image post-process.After some simulation and verification, includes VCS simulation, STA, logic synthesis and formal verification, obtains this IP in the 32-bit AHB system to be possible to achieve more than 100MHz operating frequency, also can guarantee the QVGA(320x240) dynamic revolution band width, has satisfied the design request.

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CLC: > Industrial Technology > Radio electronics, telecommunications technology > Microelectronics, integrated circuit (IC) > ASIC
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