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VLSI Design of a Small-area RSA Encryption Engine
Author: GuoWenPing
Tutor: LiuZhengLin
School: Huazhong University of Science and Technology
Course: Microelectronics and Solid State Electronics
Keywords: VLSI Design RSA algorithm Modular multiplication Modular exponentiation
CLC: TN918.2
Type: Master's thesis
Year: 2009
Downloads: 20
Quote: 0
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Abstract
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Asymmetric key algorithms are widely used in areas such as data encryption and digital signatures , and the in many asymmetric key algorithm , RSA is widely recognized as the most mature and complete algorithm . However, because of the complexity of the algorithm , the hardware overhead has been unable to meet the cost and power consumption requirements of embedded systems such resource-constrained environment applications . For this , the paper designed a used in resource-constrained environment of the small area of ??the RSA hardware encryption engine , and ASIC implementation . The paper first in-depth analysis of the various implementations of the RSA algorithm , and compare the pros and cons of their area, performance , and thus take into account the principle of the area and the encryption speed improved base 2 Montgomery modular multiplication algorithm and square - and - by the algorithm as the realization of the modular multiplication and modular exponentiation algorithm designs and implements the RSA hardware encryption engine . Encryption engine design with 256 -bit data width processing of 1024 instead of the traditional width data processing , streamlined circuit structure by folding the data channel , and the use of on-chip SRAM , reduce the realized area ; addition, the RSA core module 4- input adder , with optimized carry save adder , and by optimizing the critical path delay , to raise the maximum operating frequency . This paper to achieve a small area of ??RSA VLSI design , EDA tools for logic simulation , FPGA validation and comprehensive , complete layout using the HHNEC 0.25um CMOS standard cell library , and successfully taped . The analysis results show that the RSA 1024 -bit key length hardware encryption engine , the size of the entire design is about 24K equivalent gates , the maximum operating frequency of 100MHz , deal with a set of 1024 data encryption and decryption takes 275ms . Practical chip compared to Siemens SLE66CX160S, this realization the area is reduced by 55.63% and reached the level of practical application of the chip .
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CLC: > Industrial Technology > Radio electronics, telecommunications technology > Communicate > Confidentiality of communications and communications security > Password, machine
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