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LDPC Technology Research and Applications in Broadband Mobile Communications

Author: ZouHaiYan
Tutor: TianHui；KangGuiXia
School: Beijing University of Posts and Telecommunications
Course: Circuits and Systems
Keywords: Gbps LDPC Quasi- parallel decoding structure UMP BP-based algorithm FPGA implementation
CLC: TN929.5
Type: Master's thesis
Year: 2010
Downloads: 95
Quote: 2
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Abstract


The fourth-generation mobile communication system in recent years, attracted widespread attention in the international . China also launched FuTURE plan Gbps major project to study the key technologies of 4G mobile communication system . LDPC (Low Density Parity Check, Low Density Parity Check ) code for its excellent performance , simple form and good prospects for the application of increasingly attracting the attention of the majority of the researchers . The main task of this paper is to complete the high-performance LDPC decoder FPGA (Field Programmable Gate Array, field-programmable gate array) to implement the design . The main contents of this paper is summarized as follows: Based on BP (Belief Propagation Belief Propagation ) algorithm and LLR BP (Log-Likelihood-Ratio Belief Propagation) algorithm theoretical analysis , structured LDPC code UMP BP_based (Uniformly Most Powerful Belief -Propagation-Based) algorithm. The algorithm takes into account Gbps system engineering applications , using a layered messaging mechanism , and simplify the operation of the check node decoder . The simulation results show that the performance of the algorithm with BP algorithm fairly , can reduce the computational complexity and storage space , a better compromise between performance and complexity decoding algorithm . Then proposed a high- throughput , low- complexity LDPC quasi- parallel decoding scalable architecture and implementation of the program , and the corresponding expansion for different code length of the non- regular structured LDPC codes . UMP BP-Based Decoding Algorithm , by optimizing the common part of the parallel decoding structure of two data blocks at the same time operation, the full use of the hardware resources, and thereby improving the throughput of the decoder . Using Xilinx Virtex-5 SX95t FPGA implementation results show that : the decoder in the information throughput of up to 18 iterations 344.9MbpS . The LDPC code technology has broad application prospects . In this paper, LDPC codes and OFDM ( Orthogonal Frequency Division Multiplexing , Orthogonal Frequency Division Multiplexing ) system , can play a positive role in the next step of the research work .

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CLC: > Industrial Technology > Radio electronics, telecommunications technology > Wireless communications > Mobile Communications
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