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The Discrete Fourier Transform (DFT) is a basic digital signal processing , is the most important operations , it is widely used in many fields , has important theoretical and practical values ??. This thesis is based on the new algorithm to transform thinking , based on the first moment multiplication fast first moment DFT Professor Liu Jianguo , design a multiplication operation systolic array structure and implemented on Xilinx FPGA . This design algorithm unified , simple structure , easy to expand , the speed is relatively fast , and can meet the characteristics of any length DFT . This thesis, based on first-order moments of realization the DFT theoretical knowledge of mathematical transformations , implemented on FPGA integrated to achieve the result of the analysis based on the first-order moments of the DFT , provide the basis for the first moment other fast transform . Around this goal , the use of a hardware description language VerilogHDL, integrated design tool commonly used simulation tool ModelSim, Xilinx ISE and MATLAB , the detailed design of the pre-processing module , the first moment systolic array module , control module and twiddle factor module , and detailed design test platform , each module prior to simulation and timing analysis , the final combination of the two DFT systolic array structure , no multiplication DFT analysis by the integrated simulation results obtained this way to meet the design requirements , with good prospect of application .
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