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Storage System Design in Solid State Disk Based PCI Express Interface

Author: HuHongLiang
Tutor: ZhaoKaiWen
School: Huazhong University of Science and Technology
Course: Computer System Architecture
Keywords: Solid State Drive PCI Express bus DDR3 memory Driver Flash
CLC: TP333
Type: Master's thesis
Year: 2011
Downloads: 91
Quote: 0
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Abstract


The solid state drive compared to traditional mechanical hard more and more people of all ages because of its superior read and write performance . Currently, the mainstream SATA interface SSD read and write speeds only 200MB / S about the PCI Express 1.0 specification to its peak bandwidth of 2.5Gbps per channel and a good choice for the the SSDs development of high-speed transmission . Due to the nature of the good read and write performance of NAND Flash memory chip , non-volatile , longer service life and greater storage density , most solid-state hard drive using it as a storage carrier . Performance PCI Express bus interface as a solid-state drive storage system interface design method . First PCI Express interface features and NAND Flash read, write and erase characteristics necessary to analyze for clues to the various functional modules in the solid-state drive storage system control function modules and memory function module design . SSD internal task scheduling , resource allocation , and management of data transmission and the corresponding command parsing . In order to take full advantage of the high bandwidth of the PCI Express interface , the proposed double buffer design as a solid-state hard disk memory devices , through the link into the ring buffer not only reduces the response time of the read data and improve the use of large-capacity DDR3 SDRAM the parallelism of the data transmission , thereby sufficiently improve the data transfer speed of the solid state hard drive with the host system . Chained DMA for data transfer, relative to ordinary DMA , to further improve the efficiency of data transfer between the PCI Express interface and DDR3 SDRAM . Finally , the analysis of the design method of the the PCIE device drivers in the Linux operating system , the design of the main data structures and functions . PCI Express device driver under the Linux operating system (fedora 13) . By the test , the host system to the the DDR3 SDRAM cache data transmission speed reached 1.25GB / S, has far exceeded this speed SATA interface SSD transfer speeds, and can meet the requirements of high-speed data transmission .

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CLC: > Industrial Technology > Automation technology,computer technology > Computing technology,computer technology > Electronic digital computer (not a continuous role in computer ) > Memory
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