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Design and Implementation of High Speed Data Acquisition System for Radar Altimeter Echo Wave

Author: MaRuoFei
Tutor: HuXiuLin
School: Huazhong University of Science and Technology
Course: Communication and Information System
Keywords: High - speed data acquisition Compact PCI FPGA FIR filter
CLC: TP274.2
Type: Master's thesis
Year: 2011
Downloads: 18
Quote: 0
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Abstract


This article describes a high-speed data acquisition system based on Compact PCI bus , the system is used for real-time acquisition of pulse radar altimeter video echo signal , can also be used for other general-purpose data acquisition applications ; System sampling rates up to 200MSPS quantization precision 12bit, and static distortion of less than 0.3 % of the analog signal . Currently , high-performance data acquisition system design and implementation difficulty is not the signal of the high-speed sampling , but in the real-time processing , transmission and storage of data ; conventional storage media tend to have a lack of speed or capacity , while the data to the computer system the transmission also tend to be affected by the bus speed, and the operating system in response to the impact of the delay and other factors , and these have become the bottleneck to limit the data acquisition system performance improvement . After a lot of analysis and evaluation work , the subject decided to adopt a high-performance FPGA implementation of real-time data processing , and in accordance with the parameters of the system design and realization of a multi-level data cache system , between the ADC sampling data and Compact PCI bus Compact PCI bus adapter , then with 32bit/33MHz configuration and RAID 0 configuration disk array to achieve high-speed data transmission and storage . First, the basic principle and structure of the data acquisition system are described , and then according to the parameters of the system requirements to determine the overall program , and the parameters were calculated and demonstration ; then with a lot of space on the system hardware design FPGA logic design driver under Windows , as well as the application's design and concrete realization of the complete discussion ; Compact PCI bus operation and operating system interrupt response characteristics , based on FPGA chip RAM chip FIFO and the host physical memory multi - level data cache system and efficient data split restructuring mechanism system elaborated .

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CLC: > Industrial Technology > Automation technology,computer technology > Automation technology and equipment > Automation systems > Data processing, data processing system > Data collection and processing systems
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