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100G Ethernet PCS sublayer and its implementation in FPGA

Author: ZhangLiPeng
Tutor: ZhuQingXin
School: University of Electronic Science and Technology
Course: Applied Computer Technology
Keywords: Ethernet PCS Layer 100 Gigabit Multi-channel distribution FPGA
CLC: TN791
Type: Master's thesis
Year: 2010
Downloads: 165
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The rapid development of video services led to rapid growth of demand for network bandwidth, the backbone network is facing increasing pressure on bandwidth growth, in addition to Ethernet telecom applications also contributed to the aggregate bandwidth demand growth intensified. At present, at the level of the single-channel 100G transmission technology, indicated the era of 100G transmission. 100G Ethernet (100GE, 100 Gigabit Ethernet) is the Ethernet world, latest research technology, which not only Gigabit Ethernet rate ratio increased by 10 times, but also in the scope of application has also been more promotion. 100GE applies not only to all the traditional local area network applications, more traditional Ethernet technology extends to restricted areas of MAN and WAN. This paper describes the content is based on field programmable logic array (FPGA) for IEEE 802.3 100G Ethernet PCS (Physical Coding Sublayer) sub-layer functions are implemented. First introduced the 100G Ethernet related content, focusing on the analysis of the 100G Ethernet PCS sublayer functions and key technologies, and finally focuses on the PCS sublayer of the FPGA design and implementation, simulation and testing. Introduction of multi-channel distribution (MLD, Multi_lane Distribution) mechanism, PCS sub-layer coded data distribution to multiple logical channels, these logical channels are called virtual channel (Virtual Lane), in the current technology and process conditions to solve adaptation different physical channels or wavelengths of light problem, is the core of this design and implementation mechanisms. Through the analysis of the principle scrambling to achieve an arbitrary characteristic polynomial, arbitrary N-bit parallel self-synchronizing scrambling algorithm, and can be arbitrary characteristic polynomial calculus, arbitrary N-bit parallel frame synchronization scrambling algorithms. The method uses recursive method directly derived N clock cycles after the state of the encoder value and the current value of the encoder state logical relationship between. The logic operation is fast and simple, very conducive to hardware implementation. Given the above theory in 100G Ethernet 640bits self-synchronizing scrambling algorithm FPGA. Design process using a top-down approach gradually broken down, first overview of the entire PCS sublayer internal structure module division, followed by the design of each module is described in detail, and finally gives the testing program, verification data achieve results and timing simulation of Fig. Design uses hardware description language VerilogHDL, in the development of tools to complete Xilinx ISE 9.2.03i soft core synthesis, layout, assembly, and QuestaSim in Xilinx ISE 9.2.03i conducted timing simulation, finally downloaded to Xilinx's Virtex-5 LX330T development board for testing and validation. In the process of system architecture, the module how rational division between the various modules and how they work together to do a careful scrutiny. In the code design, try to consider the hardware implementation, fully taking into account the internal resources of the FPGA chip utilization and Verilog language can be executed concurrently design philosophy, and strive to achieve the small size and fast, in order to better meet product cost, performance and practical of the requirements.

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CLC: > Industrial Technology > Radio electronics, telecommunications technology > Basic electronic circuits > Digital circuits > Logic circuits
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