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Research and Design for CDR in Ultra High-speed Optical Fiber Communication Systems

Author: ZhaoLiShuang
Tutor: LeiZuoMing
School: Huazhong University of Science and Technology
Course: Microelectronics and Solid State Electronics
Keywords: Clock and data recovery circuit Phase-locked loop Optical fiber communication Receptor
CLC: TN929.11
Type: Master's thesis
Year: 2011
Downloads: 40
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With the increasing amount of communication data , communication system and continuously improve , has the advantages of high-speed , large capacity and long-distance transmission of optical fiber communication has become one of the most important means of transmission of today 's high-speed transmission network . Clock and data recovery circuit , bear fiber communication system clock recovery and data retiming output , restricting the speed and transmission quality of fiber optic transmission systems , has become the focus of today 's scientists and engineers who study hotspot . This paper studies the clock data recovery circuits for ultra-high-speed optical fiber communication systems , the use of \First, studies of the different existing structure in the clock data recovery circuit , and these structures were summarized and contrast , eventually using a clock data recovery circuit of the analog PLL structure ; Secondly, the depth study of the various modules of the clock data recovery circuit based nonlinear Alexander phase LC oscillator , the second-order loop filter system-level design and simulation , and gives the eye diagram of the recovered data to verify the correctness of the system ; final design unit circuit simulation . The focus of this research is to clock data recovery circuits circuit design , detailing Alexander phase detector improved sub- circuit of the LC oscillator output interface circuit , and the special structure used in ultra - high-speed system circuit design process , and ultimately to showing a simulation result of the circuit , and analyzed . SMIC 90nm Mixed Signal LowLeakage RF 1.2/1.8/3.3V (1P2M ~ 1P9M) technology on the basis of previous studies , Matlab, Hspice and SpectreRF circuit design and simulation . Simulation results show that the transmission data using the case of length 27-1 10Gbps transmission rate of the NRZ pseudo-random data , the unit circuit is able to meet the design requirements of the system , the system is able to achieve lock , and to recover the system clock of 10 Gbps , and having compared small jitter 9pspp, the the timing output data , the simulation results show that the design achieves the requirements .

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CLC: > Industrial Technology > Radio electronics, telecommunications technology > Wireless communications > Lightwave communications, laser communications > Optical fiber communication
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