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Research and Design of FFT Processor for MIMO-OFDM Applications

Author: ZhangLi
Tutor: ZouXueCheng
School: Huazhong University of Science and Technology
Course: Microelectronics and Solid State Electronics
Keywords: FFT / IFFT IEEE 802.16e MIMO-OFDM High throughput
CLC: TN919.3
Type: Master's thesis
Year: 2011
Downloads: 20
Quote: 0
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With the rapid development of mobile communications and wireless technologies , the increasing demands of the information transmission rate and transmission quality . MIMO-OFDM technology combines the advantages of OFDM and MIMO technologies can greatly increase channel capacity and improve information transfer rates and reliability , and can be effective against frequency selective fading channel , this technology has been applied in the IEEE 802.16e standard physical layer , to provide wireless broadband access service . The FFT processor is the core of one of the modules in the MIMO-OFDM system , its function is to realize the OFDM modulation, the data modulation on each sub-carrier of the system is complete . FFT processor algorithm and the hardware implementation of the pros and cons of a direct impact on the performance and cost of the system-on-chip MIMO-OFDM . 256 points for MIMO-OFDM systems based on the IEEE 802.16e standard , the paper presents a high- throughput , support 4-way parallel data path pipelined IFFT / FFT processor . This article introduces a variety of FFT algorithm and common FFT processor architecture , and in-depth analysis and comparison , select the Cooley-Tukey -4 algorithm as the realization of the FFT processor algorithm uses a pipelined architecture to design the FFT processing , and the introduction part is parallel processing, and to improve the throughput of the processor . Secondly, the detailed design of the FFT processor , including the design and optimization of the sub-module of the butterfly operation unit , a storage unit , the data in the reformer unit , the address generation unit , the master unit and the like . Finally, the processor RTL level and functional simulation and synthesis . In this paper, the design of the processor using TSMC 0.13μm process integrated Synopsys Design Compiler , the maximum operating frequency of the processor to 123 MHz , an area of ??2.16 mm2 . When the processor operating frequency of 64MHz , the throughput of 82.9 Mbps, which has to meet the throughput demands required by the system . The clock cycle of the processor to complete the 256-point complex FFT operation requires 260 . The experimental results show that the FFT processor design in this paper can meet the requirements of MIMO-OFDM systems based on the IEEE 802.16e standard .

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CLC: > Industrial Technology > Radio electronics, telecommunications technology > Communicate > Data communication > Data transmission technology
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