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DDR2 Controller Design Applied to SSD

Author: LaiHaiSheng
Tutor: LiuZhengLin
School: Huazhong University of Science and Technology
Course: IC Engineering
Keywords: Solid State Drive DDR2 controller Data calibration Bandwidth utilization
CLC: TP273
Type: Master's thesis
Year: 2011
Downloads: 48
Quote: 0
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Abstract


With the accelerating speed of the CPU , the traditional mechanical hard disk read and write speed is more and more obvious bottleneck effect , which led to the development of a solid-state hard drive . Can be expected in the near future , SSDs will be large-scale applications . Mainstream SSD storage media for Flash, when after more than a certain number of erase Flash storage reliability decreases rapidly , and Flash data transmission speed is much smaller than the solid-state hard drives external data transfer speed . DDR2 SDRAM ( DOUBLE DATE Rate Two Synchronous Dynamic Random Access Memory , a second generation of double data rate synchronous dynamic random access memory) as a cache, not only able to solve the problem of inconsistency of the transmission rate , and the write operation by merging introduced in the solid state hard drive , reduce the the Flash write endurance , and thus extend the life of the Flash . DDR2 JEDEC standard for DDR2 controller functional division , and uses the hardware description language to achieve the function of each module . Analyzes focus as well as the difficulty of the DDR2 controller design where - data calibration and use of a four-step calibration to achieve the conversion of the read data from the Data Selector pulse clock domains to the system clock domain . Combined with the application of solid-state drive , by analyzing the relationship between the timing and performance of DDR2 DDR2 controller performance optimization , reducing the power consumption of DDR2 at the same time improve the the DDR2 bandwidth utilization . Using the pipeline technology , the hidden read - write address comparison , the processing time profile to accelerate the processing speed of the DDR2 controller . Built - in self - test module provides two test mode can be used to test DDR2 chip is good or bad . To build the structure of the test platform , simulation DDR2 controller , greatly shorten the time of verification of the DDR2 controller . FPGA to verify the correctness of the controller logic part of the function . Mixed Nanosim-VCS simulation all-digital DLL delay chain of functional correctness .

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