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Research and Design of Unified Shader with Automatic Scheduling of Threads and VLIW

Author: SunGangDe
Tutor: LuoXiaoHuaï¼›DingYong
School: Zhejiang University
Course: Circuits and Systems
Keywords: GPU Shader Unified Architecture Automatic Threading Scheduling Mechanism Very Long Instruction Word Variable Length Instruction Format
CLC: TP391.41
Type: Master's thesis
Year: 2012
Downloads: 17
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Abstract


Research on programmable 3D Graphics Processing Unit (GPU) is increasingly important in 3D graphics processing of 3G mobile terminals. Because vertex shader and pixel shader are the cores to implement the programmability of 3D GPU, design of vertex shader and pixel shader with powerful function, high performance, small area and low power consumption is of great significance. The new generation shader is researched in design of unified shader, automatic scheduling mechanism of threads and very long instruction word (VLIW) in this thesis.In the aspect of design of unified shader, a unified instruction set and unified architecture are developed, which reduces the area of GPU by 12.1%. Then, this unified shader is extended, integrating instructions and arithmetic unit for video codec to enhance the performance of media SoC processor and reduce the area of SoC.In the aspect of automatic threading mechanism, an automatic thread scheduling model based on thread, instruction is proposed. And to improve the performance of shader further, another automatic thread scheduling model based on thread, instruction and opcode is researched. At the same time, an effective way of data organization of the shader is proposed to reduce the data dependency between adjacent instructions, avoiding a large number of instruction branching.In the aspect of VLIW, the length of instructions for different applications is different, which can avoid the waste of memory and reading and writing bandwidth. The serial and parallel architecture with single operand and multiple operations in two-datapath can improve the efficiency of adjacent operations with data dependency.With these solutions and synthesized with SMIC65nm cell library, the proposed shader can process 300M vertices/or 400M pixels/s with low power consumption at 400MHz in high power efficiency and hardware efficiency.

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