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The Design and Implementation of a 12 Bits 100ksps SAR ADC Based on 0.35um Mixed-signal CMOS Technology

Author: WangXingYi
Tutor: ChenNuXing
School: National University of Defense Science and Technology
Course: Software Engineering
Keywords: SAR ADC Bandgap reference Comparator Variable gain
CLC: TN792
Type: Master's thesis
Year: 2010
Downloads: 236
Quote: 0
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Abstract


Successive-approximation -register analog-to-digital converter (SAR ADC) is sampling rate less than 5Msps secondary to the common structure of the high - resolution applications , SAR ADC resolution is generally 8-16 , low power consumption , small size and other characteristics . These characteristics make it a very wide range of applications , such as portable / battery-powered instrument input quantizer , industrial control , and data / signal acquisition , etc. . The 0.35um mixed analog-digital CMOS process to achieve a sampling rate of 100ksps, the resolution adjustable SAR ADC for the 12bit input voltage range . The main contents include the following aspects: ( 1 ) summarizes the current development of domestic and foreign ADC , analyze common ADC structure , principles and key performance parameters . Improved the system configuration of a capacitance resistance hybrid SAR ADC , the structure using the first resistor string after the partial pressure capacitance proportionally weighted summation method , greatly reducing the area of ??the chip . Design a variety of programmable circuit , making the design of the ADC function relatively complete , and can be adapted to more practical applications . In this paper, the design of programmable circuit , including a choice of multi- channel input signal SAR register clock frequency selection , control the gain magnification , and so on . 4 is designed to achieve a high precision bandgap reference circuit . The bandgap reference circuit 2.4v reference voltage for ADC Temperature Coefficient 9.4ppm / ° C , low frequency 1kHz PSRR is about - 61dB . The 0.35um mixed analog-digital CMOS process to achieve a sampling rate of 100ksps SAR ADC for the 12bit input voltage range adjustable resolution . Layout simulation results show that , in the SS, TT , FF three process corners , DNL as to ± 1LSB, INL ± 1LSB, offset error ± 4LSB . Overall ADC power consumption is about 3.2mw, layout area 0.3875mm2 .

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CLC: > Industrial Technology > Radio electronics, telecommunications technology > Basic electronic circuits > Digital circuits > Digital-analog , digital to analog conversion circuit
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