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Low-Power Physical Design Based on a Wireless Broadband Multimedia SOC Chip

Author: FuYiWei
Tutor: ChaiChangChun；ChenZuo
School: Xi'an University of Electronic Science and Technology
Course: Software Engineering
Keywords: WiMAX Low-power Clock gating Area optimization
CLC: TN47
Type: Master's thesis
Year: 2011
Downloads: 96
Quote: 1
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Abstract


Today’s system on chip (SOC) design is focus on not only the performance and area but also the power. Low-power design has become a major theme in the SOC design system.In this paper, under the WiMAX(Worldwide Interoperability for Microwave Access) technology background, low-power physical design has been finished based on a wireless broadband multimedia SOC chip. The main optimization process is using Design Compiler and Power Compiler of Synopsys to do low-power synthesis, including insertion of operand isolation, insertion of clock gating and multi-threshold voltage design. Through these methods, power consumption is reduced 183.186mW, 21.83% of total power. Then IC Compiler is used to do the design of place and route. Reducing chip area and optimization of wire length is used to achieve lower power consumption and improve chip performance.The design of these low-power technology ideas, implementation details and the strengths and weaknesses are highlighted in this paper. Finally the EDA implementations of these technologies are introduced and have been put into the digital back-end design. The optimization results before and after optimization are analyzed and compared.

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CLC: > Industrial Technology > Radio electronics, telecommunications technology > Microelectronics, integrated circuit (IC) > LSI,ultra LSI
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