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Research of SRAM-based FPGA Single Event Upset Fault Injection System

Author: WuShengTao
Tutor: HuFangMing
School: Xi'an University of Electronic Science and Technology
Course: Circuits and Systems
Keywords: SRAM -based FPGA Single Event Upset Fault injection Partial reconfiguration
CLC: TN791
Type: Master's thesis
Year: 2011
Downloads: 184
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Abstract


SRAM -based FPGA has the unique advantage of high-density , low-cost , dynamic reconfiguration , etc. , to get more and more attention in the field of aerospace . But in the space radiation environment , SRAM -based FPGA compared to other types of programmable logic devices , such as ASIC, antifuse FPGAs are more susceptible to single event effects , especially single - event upset effects (single event upset , SEU ) the impact . For SRAM - based FPGA SEU anti radiation hardening and testing method has been relatively mature theory and test experience abroad , but the related technical blockade , as well as restrictions on the test conditions and resources , the late start of the domestic research in this regard , still in the exploratory research stage . How effective testing and evaluation of SRAM -based FPGA SEU effect , and to study the SEU reinforcement technology has become an urgent problem to be solved on this basis . In this paper, the part of the Virtex FPGA heavy with the technical design and implementation of a XCV300/BQV300 fault injection tool , the tool can be SRAM -based FPGA design SEU provides rapid low-cost simulation test . Thesis of SRAM - based FPGA Single Event Effects , especially the generation mechanism of SEU mitigation techniques for analysis and research , and on the the SEU effects of simulation and test using fault injection . Secondly , according to the structure of memory SRAM - based FPGA demonstrates the feasibility of fault injection technique Flip FPGA configuration memory bits to simulate the SEU effect discussed in this article fault injection solution , and on this basis . The SelectMAP part again, around the Virtex FPGA reconfiguration technology , elaborate hardware and software fault injection tool . Finally, by using the test system for the design of a typical FPGA design circuit fault injection testing SEU sensitive bits of the test circuit to verify the effectiveness of the system test herein .

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CLC: > Industrial Technology > Radio electronics, telecommunications technology > Basic electronic circuits > Digital circuits > Logic circuits
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