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Design of Merging Unit Based on Embedded FPGA

Author: ZhouYong
Tutor: LiKaiCheng
School: Huazhong University of Science and Technology
Course: Electrical detection technologies
Keywords: Merging Unit Electronic Transformer SOPC FPGA
CLC: TM45
Type: Master's thesis
Year: 2011
Downloads: 44
Quote: 0
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Abstract


With the great development and in-depth research in smart grid related technologies, a series of digital, intelligent primary equipment and secondary equipment gradually appears one after another, some of the pilot project of digital substation also put into operation, reflecting the development direction of power system. Electronic Transformer has more advantages than traditional electromagnetic transformer, it has a wide range of applications in the construction of digital substations, a key technology in application is the communication interface between electronic transformer and secondary equipments. The study of merging Unit is a concrete realization of the technology, the emergence of merging unit simplifies the design of secondary equipment, has a very important role of information sharing and system integration within the substation.This paper firstly analyzes the prospects for the development of digital substations, compares in detail the advantages and disadvantages between the electronic transformer and electromagnetic transformer. Secondly, it analyzes the present research status of merging unit at home and aboard, and the communication interface based on IEC61850 standard. Thirdly, it proposes a system scheme which based on SOPC technology, describes the function and implementation of each module of merging unit particular.This paper narrated a merging unit based on embedded SOPC technology in two part of hardware and software, the system platform uses Nios II processor core of FPGA, customizing system-related peripherals to form a complete processor system, then study of the clock synchronization problem in-depth, we use GPS and precision crystal to make sure that synchronization clock and sampling pulse is precise. Lots of IO is a feather of FPGA, it is suitable to be designed to receive multiple channels of synchronization data. Then use the internal FIFO and two-port RAM to deal with the received data, and improve the system integration. The Nios II system collects the data and make data frame in accordance with IEC61850-9-1 protocol, and then transmits the data in time through dual Ethernet modules. Lastly through the test in designed circumstance, the dissertation proves that the model’s capability meets the requirements and has high reliability.

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CLC: > Industrial Technology > Electrotechnical > Transformers, converters and reactors > Transformer
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