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A high priority value of CMOS image sensor readout circuit design

Author: LiuXiaoLei
Tutor: SangHongShi
School: Huazhong University of Science and Technology
Course: Pattern Recognition and Intelligent Systems
Keywords: CMOS Image sensor Readout circuit Correlated Double Sampling Programmable gain amplifier
CLC: TP212
Type: Master's thesis
Year: 2011
Downloads: 80
Quote: 1
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Abstract


In recent years , CMOS image sensors (CMOS Image Sensor, CIS) with its high integration, high resolution, low power consumption, etc. has made great progress . With the growing CIS pixel array , readout speed and dynamic range (Dynamic Range, DR) continues to improve, its readout circuit are increasingly high requirements , it can be said readout circuit design has become a bottleneck in the CIS , and how design a high-priority value (figure-of-merit, FOM) readout circuit to be placed in front of us an important issue. In this paper, influence readout circuit speed, power consumption and other factors were analyzed, designed a used 1M (1024x1024) pixels CIS ( Frame Rate 20fps) in the high- priority value readout circuit . The read- out circuit by a correlated double sampling (correlated double sampling, CDS), a programmable gain amplifier (programmable gain amplifier, PGA) and the interface circuit of three sub- modules . Using TSMC 0.18um 3.3V CIS process flow sheet to complete the design and layout , simulation results show that after the readout circuit enables 1M (1024x1024) pixel CIS frame rate up to 20fps ( frames / sec ) , the dynamic range of 73.9dB. Paper focuses on the CDS and PGA design. CDS is easy to produce the traditional column FPN (Fixed Pattern Noise) noise , power and area major shortcomings , the question put forward a new CDS structure in which only one column CDS circuit amplifier , which can effectively suppress the column FPN noise while power and area than traditional designs reduced by half. In addition, we propose a simple capacitor layout , feedback coefficient, low noise, high linearity PGA structure . Designed an adjustable compensation capacitor operational transconductance amplifier (Operational Transconductance Amplifier, OTA), by compensating capacitor-adjustable OTA bandwidth and greatly reduces the PGA success. Use Nanosim simulation shows : at 25MHz sampling frequency , CDS consumes only 1mW; PGA achieve 6dB steps , 0 ~ 18dB gain range , precision 12-bit, power consumption is only 10mW; interface circuit consumes 4mW. Excellent throughout the readout circuit is 30 dB gM Hz / mW.

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