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The FPGA Implementation of RED Algorithm Based on Routers

Author: WangYaJun
Tutor: YangXiaoPing
School: Jilin University
Course: Electronics and Communication Engineering
Keywords: FPGA circuit design Active Queue Management Router RED algorithm
CLC: TP393.06
Type: Master's thesis
Year: 2011
Downloads: 65
Quote: 0
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Abstract


With the rapid development of computer network, network congestion problems ensued. Found congestion, the performance of the computer network will fall, such as response time connection growth delay increase, the decline in the effective throughput of the network. Therefore, how to solve the network congestion become a hot topic of study. Congestion Control (Congestion Control) is taken in order to prevent and avoid congestion control strategies, active queue management algorithm is an important algorithm in the router congestion control. RED algorithm is the most classic algorithm of active queue management algorithm, the algorithm to achieve environmental the RED algorithm LINUX environment to achieve and WINDOWS environments, LINUX environment to achieve general simulation of a real network environment, through simulation experiments to evaluate the performance of the pros and cons of an algorithm, but RED algorithm itself will account for part of the memory resources to the router, which in turn affects the execution speed of the algorithm, and lead to real-time network control can not be effectively met; WINDOWS implementation of RED algorithm mainly refers to RED algorithm implementation using a variety of hardware and software in the WINDOWS environment, and improve the computing speed of the algorithm, and save resources consumed in the implementation of the algorithm in the router, thereby improving resource utilization. Random Early Detection is the average queue length by detecting data stream and discard the packet with a certain probability, and thus achieve the purpose to avoid network congestion. In the actual network congestion approximation, the router randomly select the source end to notify congestion, reduce the transmission data rate before queue overflow, to ease network congestion. The algorithm is based on the FIFO queue scheduling policy, and just discard the packet is entering the router, so the use of relatively simple. Random Early Detection algorithm design to pursue four goals, the first is to minimize packet loss rate and queuing delay, followed to avoid global synchronization, again to avoid unexpected business bias, finally, in the absence of transport layer protocol efficiency with The case also can control the average queue length, in order to avoid congestion. The design is the understanding of the the RED algorithm's basic principles and the calling environment, it is to separate random early detection in FPGA hardware implementation, and then by the way of data transmission, the algorithm used in routers which. RED algorithm is divided into two formula, a formula of the average queue length, drop probability formula. FPGA circuit design, the RED algorithm to establish a standard mathematical model, divided into five modules: calculate the average queue length of the module, the packet processing module, random number generation module the counter module module, discard probability calculation module. Design details, mainly related to the variable storage and calculation accuracy, the number of registers, and register and register the connection between the signal. Congestion Control Algorithm RED its relatively low latency, throughput is relatively large and good fairness has been widely applied. This design, through the analysis of the RED algorithm implemented in the FPGA design simulation waveform graph, RED algorithm implements congestion control and management functions, and the entire design FPGA resource-consuming relatively small foundation to save storage space for the router on, quickly, effectively RED algorithm.

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