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The Design and Implementation of External Interface Circuit Based on LEON Processor

Author: HaoChunE
Tutor: XiaHong
School: North China Electric Power University (Beijing)
Course: Computer Architecture
Keywords: AHB bus WISHBONE bus LEON processor AHB-WISHBONE bus bridge
CLC: TN47
Type: Master's thesis
Year: 2011
Downloads: 56
Quote: 0
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Abstract


With the rapid development of semiconductor technology in recent years, the application of the entire digital computer system integrated on a single chip SoC (system-on-chip) technology is also increasing. The IP core is a pre-designed and has been verified with relatively independent functional unit design or integrated circuit components, it can be reused in the SoC and complex ASIC circuit module. Needed on-chip bus (On Chip Bus, OCB), can be directly connected to different IP cores, bus way data communication between IP cores. LEON processor is in recent years, is widely used in the aerospace industry, the 32-bit RISC processor, which is a configurable, comprehensive, and is suitable for applications in SOC design microprocessor core. LEON source code mountain synthesizable VHDL code, and its performance is also very good, the greater benefits of the LEON processor open source code, and follow the GNU LGPL agreement, anyone can free download on its website hardware code and development tools and related documentation, and the heads of the ASIC page. USB IP core is in the OpenCore on international organizations can download free resources, it WISHBONE bus standards. The LEON processor's internal bus AMBA AHB bus protocol to follow, if you will follow the WISHBONE bus USB IP core mount to follow AMBA AHB bus protocol LEON processor resources both on the bus that will cause the LEON processing USB IP core implements the communication with each other, i.e. the effective reuse of the IP core, so that the communication is currently the most widely used processor and use the most convenient IP core organization can easily between SoC design, which can effectively simplify . Order to be able to communicate information between the two buses, the bus bridge must be used to complete the conversion of the signal and the timing. This paper proposed and to design AHB-WISHBONE bus bridge design. And WISHBONE bus AHB bus protocol to carry out detailed and comparative analysis, find two bus architecture differences in signal timing, data width and data transmission, and then put forward a proposal to eliminate these differences, and designed on the basis of AHB-WISHBONE bus bridge. AHB-WISHBONE bus bridge in ModelSim simulation test, the test results show that the the the AHB-WISHBONE bus bridge design and implementation of this article can be effectively mount the USB IP core to LEON processor, and to achieve a data transfer function between the two .

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CLC: > Industrial Technology > Radio electronics, telecommunications technology > Microelectronics, integrated circuit (IC) > LSI,ultra LSI
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