Dissertation > Excellent graduate degree dissertation topics show

The Design and Implementation of the multi - core router dynamic memory allocator

Author: LiMing
Tutor: FuYiDe
School: Nanjing University of Technology and Engineering
Course: Applied Computer Technology
Keywords: Multicore Router Dynamic memory allocation
CLC: TP393.05
Type: Master's thesis
Year: 2011
Downloads: 20
Quote: 0
Read: Download Dissertation

Abstract


With increasing Internet applications , network traffic was explosive growth , as the switching nodes in the network router in constant development , architecture and application software to adapt to changing router needs . Dynamic memory management as a the router base module , the level of performance has an important impact on the router's processing capacity and processing capacity . Dynamic memory management performance memory allocator whether full advantage of the characteristics of their hardware and software applications , so you want to design a high-performance dynamic memory allocator , we must fully understand the characteristics of the router hardware and software structure , the router software uses memory the law , the article is based on this approach to routers dynamic memory allocator designed and implemented . This paper first describes the types of dynamic memory allocation algorithms , analyze their performance differences under different application conditions ; followed by structural features for the router hardware and software , not only used in single-core processor system can be applied to multi-core multi-threaded design a processor systems , and can be adapted to different operating systems, the dynamic memory allocator , In addition , the characteristics of the router software uses memory , distributor focused on improving the small object allocation and release rate ; once again , on the realization of the dispenser is described ; Finally, the analysis of the performance of the dispenser and verified. Proved by actual verification , the memory allocator designed to meet the application requirements of different hardware and software configurations and router , with very fast speed for a small object allocation and a high degree of efficiency in the use of bulk allocation , and general-purpose memory allocation compared to their own strengths, but the distributor speed design faster and more real-time , more suitable for multi-core router .

Related Dissertations

  1. Research of Packet Scheduling Algorithm of the Click Modular Software,TP393.05
  2. Research on Some Technologies of Multiple Constrained QoS Multicast Routing Based on Theory of Complex Networks,O157.5
  3. The Legal Analysis about Netcom Limits Router,F626
  4. Oriented parallel performance multicore SMP Cluster Simulation Technology,TP338.6
  5. The memory database cluster monitoring system design and applied research,TP311.13
  6. Research and Implement of Modularization and Distributed Router’s Control Pane,TP393.05
  7. The Research of Large-Scale Internet Topology Measurement,TP393.06
  8. Design and Implementation of a Tool for Prediction of BGP Routes in a Single Autonomous System,TP393.02
  9. Research and Implement of Modularization Distributed Routers Data Pane,TP393.05
  10. XDSL router design based on embedded Linux platform,TP393.05
  11. Dynamic - static combination of probabilistic packet marking technology,TP393.08
  12. Parallel Redundant Thread Fault-Tolerant Technology Based on Embedded Multi-Core Platform,TP302.8
  13. Design and Performence Evaluation of Router Supporting Multiply Routing Algorithm for NOC,TN47
  14. Design and Verification for Router Supporting QoS,TN47
  15. Based on a multi -core computing resource scheduling system virtual machine,TP302.1
  16. Research and Design of a Heterogeneous Multi-core Architecture for Computation-intensive Task,TP332
  17. Based on the heterogeneous multi-core multi-threaded applications System Design and Implementation,TP332
  18. Design Multi-core System Using Microblaze and Realize on the Soclib,TP332
  19. Study on Multi-core-based Parallel Processing of Parallel Discrete Event Simulation,TP332
  20. E1 Interface Design Based on FPGA in Ethernet Switch Router,TP334.7
  21. Inter-AS VPN technology design and implementation,TP393.1

CLC: > Industrial Technology > Automation technology,computer technology > Computing technology,computer technology > Computer applications > Computer network > General issues > Network equipment
© 2012 www.DissertationTopic.Net  Mobile