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Design of Video Scaling Module in Video Signal Processing Chip

Author: LiYi
Tutor: ZhengXueRen
School: South China University of Technology
Course: Microelectronics and Solid State Electronics
Keywords: Video image scaling Four point three cubic interpolation Four-point piecewise interpolation Bilinear interpolation
CLC: TP391.41
Type: Master's thesis
Year: 2011
Downloads: 60
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Abstract


The video signal processing technique is the core technology of the digital TV , while the size of the zoom function of the video image is an important part of the video signal processing art , and so the size function scaling technology research variables with deep scientific and economic value . This thesis comes from the the Shenzhen Municipal Echo (ARK) Innovative Microelectronics Co., Ltd. video processing chip ARK3518 of . ARK3518 is a 32-bit AMBA AXI bus - based video processing chip SOC . This article through research , comparison and analysis of existing video image scaling algorithm suitable ARK3518 video processing chip scaling algorithms and hardware implementation architecture , the video scaling module Finally, simulation and verification of results . This article select the focus on a four-point the Bicubic interpolation algorithm , and its structure is simple row scaling and column scaling , horizontal and vertical separation can be achieved , and has become the mainstream of the video processing chip scaling module algorithm . Due to the consumption of hardware resources , based on a segmented interpolation algorithm based on the improvement of the structure of four points . Compared to a four-point the Bicubic interpolation algorithm , the algorithm in the row scaling using a four-point piecewise parabolic interpolation algorithm , each the column scaling module on the use of the two-point linear interpolation algorithm , the line scaling and column scaling save two multipliers , to the purpose to save hardware resources . Such image processing algorithms have the same good quality , worthy of study and application . Second, the article describes a video input module supports a variety of input formats and a variety of functions , signal before scaling processing , the first of its pre-treatment and storage . Finally, a more detailed description of the AHB and AXI bus protocol and works the to control ARK3518 chip work . This article is divided according to the different functions of the system from the top-down logic design method (Top-Down) , each logic module , and then use the RTL level Verilog HDL language module code using C language software functional simulation , logic synthesis and FPGA hardware verification process , so far , the project has been completed FPGA verification .

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CLC: > Industrial Technology > Automation technology,computer technology > Computing technology,computer technology > Computer applications > Information processing (information processing) > Pattern Recognition and devices > Image recognition device
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