Dissertation > Excellent graduate degree dissertation topics show

Research and Design of SAR echo signal storage system

Author: WangDong
Tutor: LvYouXin
School: University of Electronic Science and Technology
Course: Signal and Information Processing
Keywords: SAR large capacity and high-speed storage FPGA SATA DDR2 SDRAM
CLC: TN957.51
Type: Master's thesis
Year: 2011
Downloads: 42
Quote: 0
Read: Download Dissertation

Abstract


Synthetic Aperture Radar (SAR) generates a lot of high-speed raw echo data at work, and a complete record of these data is the key to post-imaging. This requires that echo data storage system should meet requirements of large capacity, high-speed, full storage, at the same time it should possess the characteristics of field operations.In view of the above problems, this dissertation studies the high speed and large capacity data storage system which is based on RAID0 disk array. This system records the whole SAR raw echo signal by using high-speed data distribution and high-speed ping-pong technology. Using high-speed data distribution technology, this system isochronously divides the 600MB/S high-speed data stream from acquisition module for radar echo into three roads, with the aim to reducing each channel data rate and storage capacity requirements. Using three SSD HD of large capacity to compose RAID0 array, the system can meet every road 200MB/S data storage rate and storage capacity of 1.5TB. Through direct construction of the disk array interface, this system is featured with being work offline, miniaturization, light-duty and being adapt to field operations. It is based on modular design to improve system later performance updates ability. Based on the study of data storage technology and approach of its FPGA-based implementation, this dissertation first proposes the whole system solution, theoretically calculates and verifies the feasibility; second gives a comprehensive exposition of module function and realization methods of the high-speed and large capacity data storage system; finally uses Verilog HDL hardware description language to realize the design of high-speed cache module, hard disk interface module, cross-clock domain data exchange module and the overall timing control module.In the full study DDR2 SDRAM and hard disk controller chip SPIF233A control method, according to the project reality, this dissertation builds functional simulation device model and finishes related functions by using some software such as Modesim 6.2 and QuartusII 9.0. As a result, key functional simulation results are given and the correctness of each module is verified. Combined with the design progress, this dissertation further verifies the reliability of each module through proper timing constraints and timing simulation.

Related Dissertations

  1. Research on Electromagnetic Acoustic Transducer Detection System Based on FPGA,TH878.2
  2. Study on Drive and Control System of Five-Phase PMSM Based on FPGA,TM341
  3. Development of LXI Arbitrary Waveform Generator,TM935
  4. Design of Digital Predistorter for RF Power Amplifier Based on FPGA,TN722.75
  5. Synchronization and Channel Estimation Algorithm in Bursted OFDM System and Its Implementation on FPGA,TN919.3
  6. Performance Analysis of Anti-Multipath Capability in DSSS System and Study on the Compensation Methods,TN914.42
  7. Research on the Super-resolution Technologies of Polarimetric SAR Images,TN957.52
  8. Optimizing and Realising Research on Vedio Compression in TV Guidance System,TN919.81
  9. Research and Hardware Simulation of Multiuser Spread Spectrum Code Acquisition Based on FPGA,TN914.42
  10. Research on Basic Algorithms of Digital Image Processing and Implementation with FPGA,TP391.41
  11. Research of High Speed Image Pre-processing System Based on FPGA,TP391.41
  12. Design of High-Speed Digital Image Acquisition and Interface Based on FPGA,TP274.2
  13. Development of Inductance Sensor Data Acquisition System Based on FPGA,TP274.2
  14. Development of Vxibus Common Interface Module Based on DSP,TP274
  15. Development of Serial Bus Analyzer Based on Nios,TP274
  16. Development of PMC High-speed Data Transmission Board Design Based on FPGA-RocketIO_X,TP274.2
  17. Development of Pxibus High Performance Digital I/O Module,TP274
  18. Development of LXI Counter,TP274
  19. A High-Speed and Real-Time Data Acquisition System Based on FPGA,TP274.2
  20. Synthesis and Fungicidal Activity of 2-Acyloxycycloalkylsulfonamides,S482.2
  21. Research on Super-resolution Reconstruction in SAR Image,TN957.52

CLC: > Industrial Technology > Radio electronics, telecommunications technology > Radar > Radar equipment,radar > Radar receiving equipment > Radar signal detection and processing
© 2012 www.DissertationTopic.Net  Mobile