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FPGA - based radar target one-dimensional distance image recognition

Author: ZhaoWen
Tutor: ZuoHeng
School: University of Electronic Science and Technology
Course: Access to information and detection technology
Keywords: HRRP Target recognition FPGA PCI Express Feature subspace
CLC: TN791
Type: Master's thesis
Year: 2011
Downloads: 44
Quote: 1
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Abstract


Radar Target Recognition (RTI) is one of the important development direction of modern radar applications , widely used in military and civilian life , especially for the modern war between ourselves and the enemy target in the investigation to identify . Fast and accurate target recognition theory and real-time implementation of the technology to a high demand for radar target recognition . In recent years , with the rapid development of the programmable logic device technology , high-density , high-performance , high - bandwidth , programmable logic devices to provide a good platform for high-speed transmission and real-time processing of radar data , real - time radar target recognition technology change was feasible , but also promote the development of radar target recognition theory and technology to the deeper . Based on the high - range resolution radar target HRRP feature subspace target recognition method based on FPGA technology to achieve research to achieve the high-speed transmission of radar data from the host to the FPGA chip memory and PCI Express high-speed bus . This paper : 1 Overview of pattern recognition theory and characteristics of the sub- space theory , and based on the characteristics of the sub - space radar target recognition algorithms are introduced . Elaborate PCI Express bus protocol and its FPGA implementation process research FPGA-based PCI Express bus data transfer implementation process . To real-time and accuracy requirements for radar target recognition , this paper single- precision floating-point processing , FPGA implementation of single precision floating point adder and accumulator , the 256-point single- precision floating-point FFT FPGA design . The completion of the the feature subspace target recognition algorithms including pretreatment subspace projection and classification and identification FPGA programming and simulation . Altera Corporation Stratix Ⅱ GX PCI Express development board designed hardware test and debug the correct recognition system design . Pass the test , to achieve high-speed transmission of radar data based on the PCI Express bus interface , complete real-time to achieve target recognition algorithm based on the characteristics of subspace . The recognition algorithms FPGA to achieve high processing accuracy the 80.3μs time target recognition process and to achieve the rapid identification of high-precision processing and target recognition algorithms radar target .

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CLC: > Industrial Technology > Radio electronics, telecommunications technology > Basic electronic circuits > Digital circuits > Logic circuits
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